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Searched refs:MI_FLUSH_DW_STORE_INDEX (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c194 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; in mi_flush_dw()
380 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; in gen6_emit_breadcrumb_xcs()
401 MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; in gen7_emit_breadcrumb_xcs()
H A Dgen8_engine_cs.c95 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; in gen8_emit_flush_xcs()
389 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; in gen12_emit_flush_xcs()
H A Dintel_gpu_commands.h166 #define MI_FLUSH_DW_STORE_INDEX (1<<21) macro
/linux/drivers/gpu/drm/xe/instructions/
H A Dxe_mi_commands.h51 #define MI_FLUSH_DW_STORE_INDEX REG_BIT(21) macro
/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_cmd.c39 MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; in pxp_emit_session_selection()
/linux/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c361 .mask = MI_FLUSH_DW_STORE_INDEX,
405 .mask = MI_FLUSH_DW_STORE_INDEX,
442 .mask = MI_FLUSH_DW_STORE_INDEX,
/linux/drivers/gpu/drm/xe/
H A Dxe_ring_ops.c119 MI_FLUSH_DW_STORE_INDEX; in emit_flush_invalidate()