Searched refs:MIPI_RX_ANA1C_CSIXA (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-mipi-csi-0-5.c | 43 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
44 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
50 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
51 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
62 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_IS, 1); in mtk_phy_csi_dphy_ana_eq_tune()
63 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_BW, 1); in mtk_phy_csi_dphy_ana_eq_tune()
69 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_IS, 1); in mtk_phy_csi_dphy_ana_eq_tune()
70 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_BW, 1); in mtk_phy_csi_dphy_ana_eq_tune()
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| H A D | phy-mtk-mipi-csi-0-5-rx-reg.h | 43 #define MIPI_RX_ANA1C_CSIXA 0x001c macro
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