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Searched refs:MES_PIPE_INST (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v12_1.c162 struct amdgpu_ring *ring = &mes->ring[MES_PIPE_INST(xcc_id, pipe)]; in mes_v12_1_submit_pkt_and_poll_completion()
163 spinlock_t *ring_lock = &mes->ring_lock[MES_PIPE_INST(xcc_id, pipe)]; in mes_v12_1_submit_pkt_and_poll_completion()
294 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); in mes_v12_1_add_hw_queue()
355 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); in mes_v12_1_remove_hw_queue()
666 int master_xcc_id, inst = MES_PIPE_INST(xcc_id, pipe); in mes_v12_1_set_hw_resources_1()
758 mes->event_log_gpu_addr + MES_PIPE_INST(xcc_id, pipe) * AMDGPU_MES_LOG_BUFFER_SIZE; in mes_v12_1_set_hw_resources()
948 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); in mes_v12_1_inv_tlbs_pasid()
992 int r, inst = MES_PIPE_INST(xcc_id, pipe); in mes_v12_1_allocate_ucode_buffer()
1027 int r, inst = MES_PIPE_INST(xcc_id, pipe); in mes_v12_1_allocate_ucode_data_buffer()
1062 int inst = MES_PIPE_INST(xcc_id, pipe); in mes_v12_1_free_ucode_buffers()
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H A Damdgpu_mes.h73 #define MES_PIPE_INST(xcc_id, pipe_id) \ macro
H A Dgmc_v12_1.c379 adev->mes.ring[MES_PIPE_INST(inst, 0)].sched.ready) && in gmc_v12_1_flush_gpu_tlb()
H A Damdgpu_gmc.c879 if (adev->mes.ring[MES_PIPE_INST(xcc_inst, 0)].sched.ready) { in amdgpu_gmc_fw_reg_write_reg_wait()