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Searched refs:MDIO_MMD_VEND1 (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/net/phy/mediatek/
H A Dmtk-ge-soc.c403 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, in cal_cycle()
406 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in cal_cycle()
416 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, in cal_cycle()
418 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); in cal_cycle()
429 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, in rext_fill_result()
450 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, in tx_offset_fill_result()
452 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, in tx_offset_fill_result()
454 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, in tx_offset_fill_result()
456 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, in tx_offset_fill_result()
510 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, in tx_amp_fill_result()
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H A Dmtk-ge.c49 phy_modify_mmd(phydev, MDIO_MMD_VEND1, in mtk_gephy_config_init()
59 phy_modify_mmd(phydev, MDIO_MMD_VEND1, in mtk_gephy_config_init()
82 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, in mt7531_phy_config_init()
87 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL, in mt7531_phy_config_init()
91 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL, in mt7531_phy_config_init()
/linux/drivers/net/phy/
H A Dmicrochip_t1.c314 { "TX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG0, 14},
315 { "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14},
316 { "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16},
317 { "TX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG4, 8},
318 { "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8},
319 { "RX ERR Count for SGMII MII2GMII", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8},
1090 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in lan887x_rgmii_init()
1097 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0, in lan887x_rgmii_init()
1104 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in lan887x_rgmii_init()
1114 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in lan887x_rgmii_init()
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H A Das21xxx.c303 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL, in aeon_firmware_boot()
308 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_FW_START_ADDR, in aeon_firmware_boot()
313 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, in aeon_firmware_boot()
319 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, in aeon_firmware_boot()
330 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in aeon_firmware_boot()
336 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in aeon_firmware_boot()
342 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in aeon_firmware_boot()
348 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL, in aeon_firmware_boot()
400 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, VEND1_IPC_STS, val, in aeon_ipc_wait_cmd()
423 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_CMD, cmd); in aeon_ipc_send_cmd()
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H A Dphy_device.c918 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
960 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
H A Dnxp-c45-tja11xx-macsec.c1608 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES, in nxp_c45_macsec_config_init()
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Daq100x.c71 int err = t3_phy_reset(phy, MDIO_MMD_VEND1, 3000); in aq100x_reset()
86 err = t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, IMASK_GLOBAL); in aq100x_intr_enable()
92 return t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, 0); in aq100x_intr_disable()
99 t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &v); in aq100x_intr_clear()
110 err = t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &cause); in aq100x_intr_handler()
292 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v); in t3_aq100x_phy_prep()
319 t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_FW_VERSION, &v); in t3_aq100x_phy_prep()
328 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v); in t3_aq100x_phy_prep()
332 err = t3_mdio_change_bits(phy, MDIO_MMD_VEND1, MDIO_CTRL1, in t3_aq100x_phy_prep()
/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
H A Dmacsec_api.c83 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
86 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
94 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
97 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
108 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
111 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, MSS_INGRESS_LUT_CTL_REGISTER_ADDR, in set_raw_ingress_record()
137 ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in get_raw_ingress_record()
142 ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in get_raw_ingress_record()
151 ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1, in get_raw_ingress_record()
157 ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1, in get_raw_ingress_record()
[all …]
/linux/drivers/net/phy/aquantia/
H A Daquantia_leds.c17 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index), in aqr_phy_led_brightness_set()
55 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index)); in aqr_phy_led_hw_control_get()
113 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index), in aqr_phy_led_hw_control_set()
122 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_DRIVE(index), in aqr_phy_led_active_low_set()
H A Daquantia_hwmon.c44 int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); in aqr_hwmon_get()
65 return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp); in aqr_hwmon_set()
70 int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); in aqr_hwmon_test_bit()
/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c680 { MDIO_MMD_VEND1, 0x8093, 0xcb5a, 0xffff }, in mv88e6393x_erratum_5_2()
681 { MDIO_MMD_VEND1, 0x8171, 0x7088, 0xffff }, in mv88e6393x_erratum_5_2()
682 { MDIO_MMD_VEND1, 0x80c9, 0x311a, 0xffff }, in mv88e6393x_erratum_5_2()
683 { MDIO_MMD_VEND1, 0x80a2, 0x8000, 0xff7f }, in mv88e6393x_erratum_5_2()
684 { MDIO_MMD_VEND1, 0x80a9, 0x0000, 0xfff0 }, in mv88e6393x_erratum_5_2()
685 { MDIO_MMD_VEND1, 0x80a3, 0x0000, 0xf8ff }, in mv88e6393x_erratum_5_2()
736 return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_VEND1, 0x8000, 0x58); in mv88e6393x_fix_2500basex_an()
/linux/drivers/net/ethernet/aquantia/atlantic/
H A Daq_phy.c165 val = aq_phy_read_reg(aq_hw, MDIO_MMD_VEND1, in aq_phy_disable_ptp()
168 aq_phy_write_reg(aq_hw, MDIO_MMD_VEND1, in aq_phy_disable_ptp()
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c1905 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, RTL8226_VND1_UNKNOWN_6A21, in rtl8226_set_mdi_swap()
2076 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); in rtl822x_set_serdes_option_mode()
2081 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, in rtl822x_set_serdes_option_mode()
2088 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); in rtl822x_set_serdes_option_mode()
2092 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); in rtl822x_set_serdes_option_mode()
2096 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); in rtl822x_set_serdes_option_mode()
2113 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_ADDR, reg); in rtl822x_serdes_write()
2117 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_DATA, val); in rtl822x_serdes_write()
2121 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CMD, in rtl822x_serdes_write()
2127 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in rtl822x_serdes_write()
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/linux/include/uapi/linux/
H A Dmdio.h32 #define MDIO_MMD_VEND1 30 /* Vendor specific 1 */ macro
189 #define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
/linux/drivers/net/dsa/mxl862xx/
H A Dmxl862xx-host.c193 return __mdiodev_c45_read(priv->mdiodev, MDIO_MMD_VEND1, addr); in mxl862xx_reg_read()
198 return __mdiodev_c45_write(priv->mdiodev, MDIO_MMD_VEND1, addr, data); in mxl862xx_reg_write()
/linux/rust/kernel/net/phy/
H A Dreg.rs173 pub const VEND1: Self = Mmd(uapi::MDIO_MMD_VEND1 as u8);
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_mdio.c20 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_read_c45()
46 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_write_c45()