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Searched refs:MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_sh_mask.h7966 #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x00800000L macro
H A Dgmc_7_1_sh_mask.h6353 #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x800000 macro
H A Dgmc_8_1_sh_mask.h7267 #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x800000 macro