| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | mt8173-rt5650.txt | 16 - mediatek,mclk: the MCLK source
17 0 : external oscillator, MCLK = 12.288M
18 1 : internal source from mt8173, MCLK = sampling rate*256
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| H A D | cs42l56.txt | 20 Frequency = MCLK / 4 * (N+2)
22 MCLK = Where MCLK is the frequency of the mclk signal after the MCLKDIV2 circuit.
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| H A D | max9860.txt | 14 - clocks : A clock specifier for the clock connected as MCLK.
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| H A D | cs43130.txt | 20 When external MCLK is generated by external crystal
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| H A D | omap-abe-twl6040.txt | 6 - ti,mclk-freq: MCLK frequency for HPPLL operation
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| H A D | da7218.txt | 25 - clocks : phandle and clock specifier for codec MCLK.
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| /linux/Documentation/devicetree/bindings/media/ |
| H A D | pxa-camera.txt | 12 sensor master clock MCLK
13 - clock-frequency: host interface is driving MCLK, and MCLK rate is this rate
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| /linux/drivers/spi/ |
| H A D | spi-mpc52xx-psc.c | 26 #define MCLK 20000000 /* PSC port MClk in hz */ macro
93 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
95 ccr |= (MCLK / 1000000 - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
250 mclken_div = 512000000 / MCLK; in mpc52xx_psc_spi_port_config()
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| /linux/sound/soc/meson/ |
| H A D | aiu-encoder-spdif.c | 144 ret = clk_set_rate(aiu->spdif.clks[MCLK].clk, mrate); in aiu_encoder_spdif_hw_params()
183 ret = clk_set_parent(aiu->spdif.clks[MCLK].clk, in aiu_encoder_spdif_startup()
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| H A D | aiu-encoder-i2s.c | 153 fs = DIV_ROUND_CLOSEST(clk_get_rate(aiu->i2s.clks[MCLK].clk), srate); in aiu_encoder_i2s_set_clocks()
283 ret = clk_set_rate(aiu->i2s.clks[MCLK].clk, freq); in aiu_encoder_i2s_set_sysclk()
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| H A D | aiu.c | 202 [MCLK] = "i2s_mclk",
209 [MCLK] = "spdif_mclk_sel"
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| H A D | aiu.h | 20 MCLK, enumerator
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| /linux/drivers/media/pci/ddbridge/ |
| H A D | ddbridge-sx8.c | 14 static const u32 MCLK = (1550000000 / 12); variable
187 if (p->symbol_rate >= (MCLK / 2)) in start()
209 if (p->symbol_rate >= MCLK / 2) { in start()
244 i = (p->symbol_rate > (MCLK / 2)) ? 3 : 7; in start()
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| /linux/arch/arm/boot/dts/st/ |
| H A D | stm32mp157c-phycore-stm32mp15-som.dtsi | 94 "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */
95 "Capture", "MCLK";
458 clock-names = "sai_ck", "MCLK";
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| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | sdm845-oneplus-enchilada.dts | 100 audio-routing = "RX_BIAS", "MCLK",
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| H A D | msm8996pro-xiaomi-natrium.dts | 107 audio-routing = "RX_BIAS", "MCLK";
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| H A D | msm8996-xiaomi-gemini.dts | 157 audio-routing = "RX_BIAS", "MCLK";
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| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | twl6040.txt | 23 - clock-names: Must be "clk32k" for the 32K clock and "mclk" for the MCLK.
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| /linux/drivers/video/fbdev/sis/ |
| H A D | init.c | 2268 SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK, in SiS_DoCalcDelay() argument
2281 idx1 = longtemp % (MCLK * 16); in SiS_DoCalcDelay()
2282 longtemp /= (MCLK * 16); in SiS_DoCalcDelay()
2289 unsigned short colordepth, unsigned short MCLK) in SiS_CalcDelay() argument
2293 temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0); in SiS_CalcDelay()
2294 temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1); in SiS_CalcDelay()
2306 unsigned short temp, index, VCLK, MCLK, colorth; in SiS_SetCRT1FIFO_300() local
2324 MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK; in SiS_SetCRT1FIFO_300()
2330 ThresholdLow = SiS_CalcDelay(SiS_Pr, VCLK, colorth, MCLK) + 1; in SiS_SetCRT1FIFO_300()
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| /linux/arch/arm/mm/ |
| H A D | proc-sa110.S | 97 ldr r1, [r1, #0] @ force switch to MCLK
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| H A D | proc-sa1100.S | 112 ldr r1, [r1, #0] @ force switch to MCLK
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | white-hawk-ard-audio-da7212.dtso | 21 * | AUDIO_CLKOUT_V pin5 |<----->| pin7 MCLK |
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| /linux/arch/powerpc/boot/dts/fsl/ |
| H A D | p1022rdk.dts | 56 /* MCLK source is a stand-alone oscillator */
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| /linux/drivers/video/fbdev/savage/ |
| H A D | savagefb.h | 210 int MCLK, REFCLK, LCDclk; member
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| H A D | savagefb_driver.c | 1087 if (par->MCLK <= 0) { in savagefb_decode_var()
1091 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000, in savagefb_decode_var()
1937 par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100; in savage_init_hw()
1939 par->MCLK); in savage_init_hw()
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