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Searched refs:MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7675 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L macro
H A Ddce_8_0_sh_mask.h8153 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 macro
H A Ddce_11_0_sh_mask.h7107 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 macro
H A Ddce_10_0_sh_mask.h7217 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 macro
H A Ddce_11_2_sh_mask.h8219 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 macro
H A Ddce_12_0_sh_mask.h5120 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h4139 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK … macro
H A Ddcn_3_0_1_sh_mask.h2846 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK … macro
H A Ddcn_2_1_0_sh_mask.h2645 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK … macro
H A Ddcn_2_0_0_sh_mask.h2913 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK … macro