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Searched refs:LOAD (Results 1 – 25 of 59) sorted by relevance

123

/linux/arch/sparc/lib/
H A DU3memcpy.S40 #ifndef LOAD
41 #define LOAD(type,addr,dest) type [addr], dest macro
215 EX_LD_FP(LOAD(ldub, %o1 + 0x00, %o3), U3_retl_o2_plus_g2_plus_g1_plus_1)
227 EX_LD_FP(LOAD(ldd, %o1, %f4), U3_retl_o2_plus_g2)
228 1: EX_LD_FP(LOAD(ldd, %o1 + 0x8, %f6), U3_retl_o2_plus_g2)
236 EX_LD_FP(LOAD(ldd, %o1 + 0x8, %f4), U3_retl_o2_plus_g2)
244 3: LOAD(prefetch, %o1 + 0x000, #one_read)
245 LOAD(prefetch, %o1 + 0x040, #one_read)
247 LOAD(prefetch, %o1 + 0x080, #one_read)
248 LOAD(prefetch, %o1 + 0x0c0, #one_read)
[all …]
H A DNG4memcpy.S65 #ifndef LOAD
66 #define LOAD(type,addr,dest) type [addr], dest macro
130 1: EX_LD(LOAD(ldub, %o1 + 0x00, %g2), memcpy_retl_o2_plus_g1)
137 51: LOAD(prefetch, %o1 + 0x040, #n_reads_strong)
138 LOAD(prefetch, %o1 + 0x080, #n_reads_strong)
139 LOAD(prefetch, %o1 + 0x0c0, #n_reads_strong)
140 LOAD(prefetch, %o1 + 0x100, #n_reads_strong)
141 LOAD(prefetch, %o1 + 0x140, #n_reads_strong)
142 LOAD(prefetch, %o1 + 0x180, #n_reads_strong)
143 LOAD(prefetch, %o1 + 0x1c0, #n_reads_strong)
[all …]
H A DM7memcpy.S116 #ifndef LOAD
117 #define LOAD(type,addr,dest) type [addr], dest macro
209 EX_LD(LOAD(ldub, %o4, %o4), memcpy_retl_o2_plus_o5) ! load one byte
236 EX_LD(LOAD(ldx, %o1, %o4), memcpy_retl_o2_plus_63) ! load
239 EX_LD(LOAD(ldx, %o1+8, %o3), memcpy_retl_o2_plus_63_56) ! a block of 64
241 EX_LD(LOAD(ldx, %o1+16, %o4), memcpy_retl_o2_plus_63_48)
243 EX_LD(LOAD(ldx, %o1+24, %o3), memcpy_retl_o2_plus_63_40)
245 EX_LD(LOAD(ldx, %o1+32, %o4), memcpy_retl_o2_plus_63_32)! load and store
247 EX_LD(LOAD(ldx, %o1+40, %o3), memcpy_retl_o2_plus_63_24)! a block of 64
250 EX_LD(LOAD(ldx, %o1-16, %o4), memcpy_retl_o2_plus_63_16)
[all …]
H A Dcsum_copy.S27 #ifndef LOAD
28 #define LOAD(type,addr,dest) type [addr], dest macro
50 EX_LD(LOAD(ldub, %o0 + 0x00, %o4))
60 EX_LD(LOAD(lduh, %o0 + 0x00, %o5))
72 LOAD(prefetch, %o0 + 0x000, #n_reads)
78 LOAD(prefetch, %o0 + 0x040, #n_reads)
91 LOAD(prefetch, %o0 + 0x080, #n_reads)
94 LOAD(prefetch, %o0 + 0x0c0, #n_reads)
97 LOAD(prefetch, %o0 + 0x100, #n_reads)
105 LOAD(prefetch, %o0 + 0x140, #n_reads)
[all …]
H A DNG2memcpy.S50 #ifndef LOAD
51 #define LOAD(type,addr,dest) type [addr], dest macro
141 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1)
143 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
144 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1);
146 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
147 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
148 EX_LD_FP(LOAD(ldd, base + 0x10, %x2), NG2_retl_o2_plus_g1);
150 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
151 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
[all …]
H A DNGmemcpy.S38 #ifndef LOAD
40 #define LOAD(type,addr,dest) type [addr], dest macro
42 #define LOAD(type,addr,dest) type##a [addr] 0x80, dest macro
202 LOAD(prefetch, %i1, #one_read)
212 EX_LD(LOAD(ldub, %i1, %g1), NG_ret_i2_plus_i4_plus_1)
266 LOAD(prefetch, %i1 + %i3, #one_read)
299 LOAD(prefetch, %i1 + %i3, #one_read)
341 LOAD(prefetch, %i1 + %o1, #one_read)
370 LOAD(prefetch, %i1 + %o1, #one_read)
408 EX_LD(LOAD(ldx, %i1, %o4), NG_ret_i2_plus_i4)
[all …]
H A DGENmemcpy.S22 #ifndef LOAD
23 #define LOAD(type,addr,dest) type [addr], dest macro
97 EX_LD(LOAD(ldub, %o1, %g1),GEN_retl_o4_1)
106 EX_LD(LOAD(ldx, %o1, %g2),GEN_retl_g1_8)
124 EX_LD(LOAD(lduw, %o1, %g1),GEN_retl_o2_4)
135 EX_LD(LOAD(ldub, %o1, %g1),GEN_retl_o2_1)
H A DU1memcpy.S42 #ifndef LOAD
43 #define LOAD(type,addr,dest) type [addr], dest macro
284 EX_LD_FP(LOAD(ldub, %o1 + 0x00, %o3), U1_g1_1_fp)
296 EX_LD_FP(LOAD(ldd, %o1, %f4), U1_g2_0_fp)
297 1: EX_LD_FP(LOAD(ldd, %o1 + 0x8, %f6), U1_g2_0_fp)
305 EX_LD_FP(LOAD(ldd, %o1 + 0x8, %f4), U1_g2_0_fp)
550 93: EX_LD_FP(LOAD(ldd, %o1, %f2), U1_g3_0_fp)
557 EX_LD_FP(LOAD(ldd, %o1, %f0), U1_g3_0_fp)
568 1: EX_LD_FP(LOAD(ldub, %o1, %o3), U1_o2_0_fp)
587 1: EX_LD(LOAD(ldx, %o1 + 0x00, %o5), U1_gs_0)
[all …]
H A Dcsum_copy_from_user.S20 #define LOAD(type,addr,dest) type##a [addr] %asi, dest macro
H A DU3copy_from_user.S24 #define LOAD(type,addr,dest) type##a [addr] %asi, dest macro
H A DGENcopy_from_user.S20 #define LOAD(type,addr,dest) type##a [addr] ASI_AIUS, dest macro
H A DNGcopy_from_user.S20 #define LOAD(type,addr,dest) type##a [addr] ASI_AIUS, dest macro
H A DNG4copy_from_user.S28 #define LOAD(type,addr,dest) type##a [addr] %asi, dest macro
H A DM7copy_from_user.S29 #define LOAD(type,addr,dest) type##a [addr] %asi, dest macro
/linux/arch/powerpc/lib/
H A Dxor_vmx.c28 #define LOAD(V) \ macro
61 LOAD(v1); in __xor_altivec_2()
62 LOAD(v2); in __xor_altivec_2()
82 LOAD(v1); in __xor_altivec_3()
83 LOAD(v2); in __xor_altivec_3()
84 LOAD(v3); in __xor_altivec_3()
108 LOAD(v1); in __xor_altivec_4()
109 LOAD(v2); in __xor_altivec_4()
110 LOAD(v3); in __xor_altivec_4()
111 LOAD(v4); in __xor_altivec_4()
[all …]
/linux/Documentation/translations/ko_KR/
H A Dmemory-barriers.txt188 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
189 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
190 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
191 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
192 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
193 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
194 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
245 STORE *A = 5, x = LOAD *D
246 x = LOAD *D, STORE *A = 5
263 Q = LOAD P, D = LOAD *Q
[all …]
/linux/arch/mips/cavium-octeon/
H A Docteon-memcpy.S84 #define LOAD ld macro
187 EXC( LOAD t0, UNIT(0)(src), l_exc)
188 EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
189 EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
190 EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
196 EXC( LOAD t0, UNIT(4)(src), l_exc_copy)
197 EXC( LOAD t1, UNIT(5)(src), l_exc_copy)
198 EXC( LOAD t2, UNIT(6)(src), l_exc_copy)
199 EXC( LOAD t3, UNIT(7)(src), l_exc_copy)
206 EXC( LOAD t0, UNIT(-8)(src), l_exc_copy_rewind16)
[all …]
/linux/arch/mips/lib/
H A Dcsum_partial.S43 #define LOAD ld macro
50 #define LOAD lw macro
76 LOAD _t0, (offset + UNIT(0))(src); \
77 LOAD _t1, (offset + UNIT(1))(src); \
78 LOAD _t2, (offset + UNIT(2))(src); \
79 LOAD _t3, (offset + UNIT(3))(src); \
367 #undef LOAD
372 #define LOAD(reg, addr) EXC(ld, LD_INSN, reg, addr) macro
392 #define LOAD(reg, addr) EXC(lw, LD_INSN, reg, addr) macro
472 LOAD(t0, UNIT(0)(src))
[all …]
H A Dmemcpy.S149 #define LOAD(reg, addr, handler) EXC(ld, LD_INSN, reg, addr, handler) macro
186 #define LOAD(reg, addr, handler) EXC(lw, LD_INSN, reg, addr, handler) macro
325 LOAD(t0, UNIT(0)(src), .Ll_exc\@)
326 LOAD(t1, UNIT(1)(src), .Ll_exc_copy\@)
327 LOAD(t2, UNIT(2)(src), .Ll_exc_copy\@)
328 LOAD(t3, UNIT(3)(src), .Ll_exc_copy\@)
330 LOAD(t4, UNIT(4)(src), .Ll_exc_copy\@)
331 LOAD(t7, UNIT(5)(src), .Ll_exc_copy\@)
334 LOAD(t0, UNIT(6)(src), .Ll_exc_copy\@)
335 LOAD(t1, UNIT(7)(src), .Ll_exc_copy\@)
[all …]
/linux/arch/arm/mach-spear/
H A Dtime.c38 #define LOAD(x) ((x) * 0x80 + 0x88) macro
81 writew(0xFFFF, gpt_base + LOAD(CLKSRC)); in spear_clocksource_init()
133 writew(period, gpt_base + LOAD(CLKEVT)); in spear_set_periodic()
162 writew(cycles, gpt_base + LOAD(CLKEVT)); in clockevent_next_event()
/linux/Documentation/
H A Dmemory-barriers.txt158 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
159 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
160 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
161 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
162 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
163 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
164 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
216 STORE *A = 5, x = LOAD *D
217 x = LOAD *D, STORE *A = 5
235 Q = LOAD P, D = LOAD *Q
[all …]
/linux/arch/arm64/net/
H A Dbpf_jit.h61 #define A64_LDRB(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 8, LOAD)
64 #define A64_LDRH(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 16, LOAD)
67 #define A64_LDR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, LOAD)
70 #define A64_LDR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, LOAD)
78 #define A64_LDRBI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 8, LOAD)
81 #define A64_LDRHI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 16, LOAD)
84 #define A64_LDR32I(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 32, LOAD)
87 #define A64_LDR64I(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 64, LOAD)
103 #define A64_POP(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, 16, LOAD, POST_INDEX)
/linux/drivers/pwm/
H A Dpwm-stmpe.c90 #define LOAD BIT(14) /* Only available on 2403 */ macro
160 program[0] = LOAD | 0xff; /* LOAD 0xff */ in stmpe_24xx_pwm_config()
168 program[0] = LOAD | 0x00; /* LOAD 0x00 */ in stmpe_24xx_pwm_config()
198 program[0] = LOAD | value; in stmpe_24xx_pwm_config()
/linux/Documentation/translations/sp_SP/
H A Dmemory-barriers.txt173 organizar en 24 combinaciones diferentes (donde LOAD es cargar y STORE es
176 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
177 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
178 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
179 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
180 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
181 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
182 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
232 STORE *A = 5, x = LOAD *D
233 x = LOAD *D, STORE *A = 5
[all …]
/linux/lib/zlib_dfltcc/
H A Ddfltcc_inflate.h26 LOAD(); \

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