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Searched refs:LANE_COUNT_DP_MAX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_fixed_vs_pe_retimer.h38 const union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX],
43 union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX]);
H A Dlink_dp_training_8b_10b.c231 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; in perform_8b_10b_clock_recovery_sequence()
233 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in perform_8b_10b_clock_recovery_sequence()
352 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in perform_8b_10b_channel_equalization_sequence()
353 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in perform_8b_10b_channel_equalization_sequence()
470 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_perform_8b_10b_link_training()
H A Dlink_dp_capability.c433 if (link->dpcd_caps.lttpr_caps.max_lane_count <= LANE_COUNT_DP_MAX) in get_lttpr_max_lane_count()
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dlink_hwss.h65 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dlink_encoder.h141 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.h284 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
H A Ddce_link_encoder.c1468 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in dce110_link_encoder_dp_set_lane_settings() argument
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h1676 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c1076 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; in poll_for_allocation_change_trigger()