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Searched refs:L3 (Results 1 – 25 of 70) sorted by relevance

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/linux/net/l3mdev/
H A DKconfig3 # Configuration for L3 master device support
7 bool "L3 Master device support"
11 drivers to support L3 master devices like VRF.
/linux/arch/x86/events/intel/
H A Dds.c126 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
130 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
131 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
132 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
133 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
134 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
135 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
137 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
147 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
148 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
[all …]
/linux/Documentation/networking/
H A Dipvlan.rst13 exception of using L3 for mux-ing /demux-ing among slaves. This property makes
42 L3 bridge mode::
61 IPvlan has two modes of operation - L2 and L3. For a given master device,
64 that in L3 mode the slaves won't receive any multicast / broadcast traffic.
65 L3 mode is more restrictive since routing is controlled from the other (mostly)
76 4.2 L3 mode:
79 In this mode TX processing up to L3 happens on the stack instance attached
88 This is very similar to the L3 mode except that iptables (conn-tracking)
89 works in this mode and hence it is L3-symmetric (L3s). This will have slightly less
90 performance but that shouldn't matter since you are choosing this mode over plain-L3
H A Dbareudp.rst7 There are various L3 encapsulation standards using UDP being discussed to
11 The Bareudp tunnel module provides a generic L3 encapsulation support for
12 tunnelling different L3 protocols like MPLS, IP, NSH etc. inside a UDP tunnel.
31 This creates a bareudp tunnel device which tunnels L3 traffic with ethertype
/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-cpus.dtsi170 next-level-cache = <&L3>;
178 next-level-cache = <&L3>;
186 next-level-cache = <&L3>;
194 next-level-cache = <&L3>;
197 L3: l3-cache { label
/linux/Documentation/admin-guide/perf/
H A Dqcom_l3_pmu.rst2 Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
5 This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
6 Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
H A Darm_dsu_pmu.rst5 ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,
7 allows counting the various events related to the L3 cache, Snoop Control Unit
H A Dxgene-pmu.rst6 L3 cache(s), I/O bridge(s), memory controller bridge(s) and memory
25 performance of a specific datapath. For example, agents of a L3 cache can be
/linux/drivers/net/ethernet/intel/libie/
H A Drx.c42 #define LIBIE_RX_PT_L3 __LIBIE_RX_PT_L2(NONE, L3)
45 LIBIE_RX_PT(IPV##oip, FRAG, NONE, NONE, NOT_FRAG, NONE, L3)
47 LIBIE_RX_PT(IPV##oip, NOT_FRAG, tun, teprot, tefr, NONE, L3)
/linux/Documentation/devicetree/bindings/sound/
H A Domap-dmic.txt7 <L3 interconnect address, size>;
16 <0x4902e000 0x7f>; /* L3 Interconnect */
/linux/arch/alpha/kernel/
H A Dsetup.c1195 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1206 L3 = -1; in determine_cpu_caches()
1227 L3 = -1; in determine_cpu_caches()
1258 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches()
1272 L3 = -1; in determine_cpu_caches()
1295 L3 = -1; in determine_cpu_caches()
1302 L3 = -1; in determine_cpu_caches()
1307 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1314 alpha_l3_cacheshape = L3; in determine_cpu_caches()
/linux/Documentation/devicetree/bindings/arm/omap/
H A Dl3-noc.txt1 * TI - L3 Network On Chip (NoC)
12 - reg: Contains L3 register address range for each noc domain.
/linux/arch/m68k/lib/
H A Ddivsi3.S117 jpl L3
120 L3: movel sp@+, d2 label
H A Dudivsi3.S95 jcc L3 /* then try next algorithm */
107 L3: movel d1, d2 /* use d2 as divisor backup */ label
/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dmemory.txt88 | | | | +-> [20:12] L3 索引
103 | | | +----------> [28:16] L3 索引
/linux/arch/riscv/lib/
H A Dtishift.S33 beqz a2, .L3
44 .L3: label
/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dmemory.txt92 | | | | +-> [20:12] L3 索引
107 | | | +----------> [28:16] L3 索引
/linux/lib/
H A Dtest_dynamic_debug.c92 enum cat_level_names { L0 = 22, L1, L2, L3, L4, L5, L6, L7 }; enumerator
135 prdbg(L3); in do_levels()
/linux/arch/arm/boot/dts/gemini/
H A Dgemini-wbd111.dts45 label = "wbd111:red:L3";
63 label = "wbd111:green:L3";
H A Dgemini-wbd222.dts44 label = "wbd111:red:L3";
62 label = "wbd111:green:L3";
/linux/Documentation/locking/
H A Drt-mutex-design.rst139 Mutexes: L1, L2, L3, L4
145 C owns L3
146 D blocked on L3
152 E->L4->D->L3->C->L2->B->L1->A
166 E->L4->D->L3->C->L2-+
185 E->L4->D->L3->C-+
230 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
231 The following shows a locking order of L1->L2->L3, but may not actually
257 mutex_lock(L3);
261 mutex_unlock(L3);
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-l4-abe.dtsi53 /* L3 to L4 ABE mapping */
110 <0x49022000 0xff>; /* L3 Interconnect */
145 <0x49024000 0xff>; /* L3 Interconnect */
180 <0x49026000 0xff>; /* L3 Interconnect */
234 <0x4902e000 0x7f>; /* L3 Interconnect */
277 <0x49032000 0x7f>; /* L3 Interconnect */
/linux/arch/xtensa/lib/
H A Dmemset.S83 bbci.l a4, 2, .L3
87 .L3: label
/linux/arch/sparc/net/
H A Dbpf_jit_64.h23 #define L3 0x13 macro
/linux/Documentation/bpf/
H A Dprog_flow_dissector.rst28 * ``n_proto`` - L3 protocol type, parsed out of L2 header
130 * ``jmp_table`` map that contains sub-programs for each supported L3 protocol
132 does ``bpf_tail_call`` to the appropriate L3 handler

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