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Searched refs:JH7110_SYSCLK_UART5_CORE (Results 1 – 3 of 3) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dstarfive,jh7110-crg.h173 #define JH7110_SYSCLK_UART5_CORE 156 macro
/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-sys.c258 JH71X0_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi678 clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,