Home
last modified time | relevance | path

Searched refs:InterlaceEnable (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h112 unsigned int InterlaceEnable; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.h670 unsigned int InterlaceEnable,
H A Ddisplay_mode_vba_util_32.c2068 myPipe[k].InterlaceEnable, in dml32_CalculateVMRowAndSwath()
2142 myPipe[k].InterlaceEnable, in dml32_CalculateVMRowAndSwath()
3203 unsigned int InterlaceEnable, in dml32_CalculateVUpdateAndDynamicMetadataParameters() argument
3232 if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) in dml32_CalculateVUpdateAndDynamicMetadataParameters()
3509 myPipe->InterlaceEnable, in dml32_CalculatePrefetchSchedule()
3591 …if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnit… in dml32_CalculatePrefetchSchedule()
H A Ddisplay_mode_vba_32.c437 …chParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].InterlaceEnable = mode_lib->v… in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
774 …eepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.InterlaceEnable = mode_lib->v… in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2730 …v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].InterlaceEnable = mode… in dml32_ModeSupportAndSystemConfigurationFull()
3279 …v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.InterlaceEnable = mode_lib->vba.I… in dml32_ModeSupportAndSystemConfigurationFull()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_mode_vba_31.c76 unsigned int InterlaceEnable; member
282 int InterlaceEnable,
935 myPipe->InterlaceEnable,
1009 if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
2607 myPipe.InterlaceEnable = v->Interlace[k];
3411 int InterlaceEnable, argument
3435 if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) {
3696 myPipe.InterlaceEnable = v->Interlace[k];
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_shared_types.h117 unsigned int InterlaceEnable; member
H A Ddml2_core_shared.c496 unsigned int InterlaceEnable,
1666 …s->SurfParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descript… in dml2_core_shared_mode_support()
2307 …myPipe->InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream… in dml2_core_shared_mode_support()
5633 p->myPipe[k].InterlaceEnable, in CalculateVMRowAndSwath()
5711 p->myPipe[k].InterlaceEnable, in CalculateVMRowAndSwath()
7287 unsigned int InterlaceEnable, in CalculateVUpdateAndDynamicMetadataParameters() argument
7313 if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) { in CalculateVUpdateAndDynamicMetadataParameters()
7602 p->myPipe->InterlaceEnable, in CalculatePrefetchSchedule()
7681 …if (p->OutputFormat == dml2_420 || (p->myPipe->InterlaceEnable && p->myPipe->ProgressiveToInterlac… in CalculatePrefetchSchedule()
10187 …s->SurfaceParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descr… in dml2_core_shared_mode_programming()
[all …]
H A Ddml2_core_dcn4_calcs.c2976 p->myPipe[k].InterlaceEnable, in CalculateVMRowAndSwath()
3054 p->myPipe[k].InterlaceEnable, in CalculateVMRowAndSwath()
4847 unsigned int InterlaceEnable, in CalculateVUpdateAndDynamicMetadataParameters() argument
4873 if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) { in CalculateVUpdateAndDynamicMetadataParameters()
5211 p->myPipe->InterlaceEnable, in CalculatePrefetchSchedule()
5292 …if (p->OutputFormat == dml2_420 || (p->myPipe->InterlaceEnable && p->myPipe->ProgressiveToInterlac… in CalculatePrefetchSchedule()
8288 …s->SurfParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descript… in dml_core_mode_support()
8986 …myPipe->InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream… in dml_core_mode_support()
10699 …s->SurfaceParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descr… in dml_core_mode_programming()
11213 …myPipe->InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream… in dml_core_mode_programming()
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddisplay_mode_core.c361 dml_uint_t InterlaceEnable,
1064 p->myPipe->InterlaceEnable, in CalculatePrefetchSchedule()
1138 …if (p->OutputFormat == dml_420 || (p->myPipe->InterlaceEnable && p->myPipe->ProgressiveToInterlace… in CalculatePrefetchSchedule()
1858 dml_uint_t InterlaceEnable, in CalculateVUpdateAndDynamicMetadataParameters() argument
1884 if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) { in CalculateVUpdateAndDynamicMetadataParameters()
5130 p->myPipe[k].InterlaceEnable, in CalculateVMRowAndSwath()
5203 p->myPipe[k].InterlaceEnable, in CalculateVMRowAndSwath()
6374 myPipe->InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k]; in dml_prefetch_check()
7658 s->SurfParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k]; in dml_core_mode_support()
8670 s->SurfaceParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k]; in dml_core_mode_programming()
[all …]
H A Ddisplay_mode_core_structs.h464 dml_uint_t InterlaceEnable; member