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Searched refs:ISHARP_LBA_PWL_SEG5 (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp.h639 uint32_t ISHARP_LBA_PWL_SEG5; member
H A Ddcn401_dpp_dscl.c1016 REG_SET_2(ISHARP_LBA_PWL_SEG5, 0, in dpp401_dscl_program_isharp()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.h402 SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id), \