Searched refs:IRQ_REG_ENTRY_DMUB (Results 1 – 10 of 10) sorted by relevance
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
H A D | irq_service_dcn31.c | 222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ macro 289 IRQ_REG_ENTRY_DMUB(\
|
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
H A D | irq_service_dcn315.c | 229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ macro 296 IRQ_REG_ENTRY_DMUB(\
|
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
H A D | irq_service_dcn32.c | 223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ macro 290 IRQ_REG_ENTRY_DMUB(\
|
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
H A D | irq_service_dcn302.c | 208 IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\ 213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ macro
|
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
H A D | irq_service_dcn30.c | 234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ macro 294 IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\
|
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
H A D | irq_service_dcn21.c | 227 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ macro 295 IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
|
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
H A D | irq_service_dcn314.c | 224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ macro 291 IRQ_REG_ENTRY_DMUB(\
|
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn401/ |
H A D | irq_service_dcn401.c | 203 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ macro 269 IRQ_REG_ENTRY_DMUB(\
|
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/ |
H A D | irq_service_dcn351.c | 200 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ macro 256 IRQ_REG_ENTRY_DMUB(DC_IRQ_SOURCE_DMCUB_OUTBOX, \
|
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/ |
H A D | irq_service_dcn35.c | 221 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ macro 277 IRQ_REG_ENTRY_DMUB(DC_IRQ_SOURCE_DMCUB_OUTBOX, \
|