| /linux/drivers/pinctrl/renesas/ |
| H A D | pfc-r8a77970.c | 128 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
210 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F… macro
284 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
596 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
597 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
598 PINMUX_IPSR_GPSR(IP5_31_28, D6),
599 PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1),
2282 IP5_31_28
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| H A D | pfc-r8a77980.c | 143 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
244 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) … macro
334 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
674 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
675 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
676 PINMUX_IPSR_GPSR(IP5_31_28, D6),
677 PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD),
2736 IP5_31_28
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| H A D | pfc-r8a77990.c | 83 #define GPSR0_2 F_(D2, IP5_31_28)
263 #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4… macro
402 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
847 PINMUX_IPSR_GPSR(IP5_31_28, D2),
848 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0),
849 PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2),
850 PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0),
851 PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3),
852 PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2),
853 PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19),
[all …]
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| H A D | pfc-r8a77995.c | 112 #define GPSR2_10 F_(VI4_DATA9, IP5_31_28)
259 #define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) … macro
376 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
712 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9),
713 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0),
714 PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1),
2723 IP5_31_28
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| H A D | pfc-r8a77965.c | 97 #define GPSR0_4 F_(D4, IP5_31_28)
307 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, … macro
465 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
953 PINMUX_IPSR_GPSR(IP5_31_28, D4),
954 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
955 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
956 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
5593 IP5_31_28
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| H A D | pfc-r8a77951.c | 92 #define GPSR0_4 F_(D4, IP5_31_28)
302 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, … macro
460 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
947 PINMUX_IPSR_GPSR(IP5_31_28, D4),
948 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
949 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
950 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
5397 IP5_31_28
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| H A D | pfc-r8a7796.c | 97 #define GPSR0_4 F_(D4, IP5_31_28)
307 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, … macro
465 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
951 PINMUX_IPSR_GPSR(IP5_31_28, D4),
952 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
953 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
954 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
5352 IP5_31_28
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| H A D | pfc-r8a77470.c | 732 PINMUX_IPSR_GPSR(IP5_31_28, DU0_DG6),
733 PINMUX_IPSR_MSEL(IP5_31_28, HRX1_C, SEL_HSCIF1_2),
734 PINMUX_IPSR_GPSR(IP5_31_28, A14),
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