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Searched refs:IP3_7_4 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c114 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
189 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0)… macro
270 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
496 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
497 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
498 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
499 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
2269 IP3_7_4
H A Dpfc-r8a77980.c129 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
223 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0)… macro
320 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
580 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
581 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
582 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
583 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
2723 IP3_7_4
H A Dpfc-r8a77990.c108 #define GPSR1_2 F_(A2, IP3_7_4)
239 #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) F… macro
387 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
675 PINMUX_IPSR_GPSR(IP3_7_4, A2),
676 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
677 PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS),
678 PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB),
679 PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0),
680 PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP),
681 PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1),
[all …]
H A Dpfc-r8a77995.c70 #define GPSR1_18 F_(DU_DR2, IP3_7_4)
235 #define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0… macro
361 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
634 PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2),
635 PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18),
636 PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2),
2710 IP3_7_4
H A Dpfc-r8a77470.c653 PINMUX_IPSR_GPSR(IP3_7_4, D15),
654 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_SS2),
655 PINMUX_IPSR_GPSR(IP3_7_4, PWM4_A),
656 PINMUX_IPSR_MSEL(IP3_7_4, CAN1_TX_B, SEL_CAN1_1),
657 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
658 PINMUX_IPSR_MSEL(IP3_7_4, AVB_AVTP_MATCH_A, SEL_AVB_0),
H A Dpfc-r8a7796.c122 #define GPSR1_10 F_(A10, IP3_7_4)
284 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, … macro
451 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
813 PINMUX_IPSR_GPSR(IP3_7_4, A10),
814 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
815 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
816 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
5339 IP3_7_4
H A Dpfc-r8a77951.c117 #define GPSR1_10 F_(A10, IP3_7_4)
281 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, … macro
446 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
809 PINMUX_IPSR_GPSR(IP3_7_4, A10),
810 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
811 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
812 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
5384 IP3_7_4
H A Dpfc-r8a77965.c122 #define GPSR1_10 F_(A10, IP3_7_4)
284 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, … macro
451 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
815 PINMUX_IPSR_GPSR(IP3_7_4, A10),
816 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
817 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
818 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
5580 IP3_7_4
H A Dpfc-r8a7790.c959 PINMUX_IPSR_GPSR(IP3_7_4, A12),
960 PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
961 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
962 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
963 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
964 PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
965 PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),