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Searched refs:IO_ADDRESS (Results 1 – 10 of 10) sorted by relevance

/linux/arch/arm/mach-tegra/
H A Dreset.c34 IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); in tegra_cpu_reset_handler_set()
35 void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); in tegra_cpu_reset_handler_set()
58 void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); in tegra_cpu_reset_handler_enable()
H A Dpm.c322 memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), in tegra_suspend_enter_lp1()
324 memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), in tegra_suspend_enter_lp1()
333 memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr, in tegra_suspend_exit_lp1()
H A Diomap.h127 #define IO_ADDRESS(n) (IO_TO_VIRT(n)) macro
H A Dplatsmp.c179 scu_enable(IO_ADDRESS(scu_a9_get_base())); in tegra_smp_prepare_cpus()
/linux/arch/arm/mach-versatile/
H A Dintegrator_cp.c39 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
44 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
49 .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
H A Dversatile.c25 #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) macro
26 #define __io_address(n) ((void __iomem __force *)IO_ADDRESS(n))
93 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
H A Dintegrator_ap.c46 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
51 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
H A Dintegrator-hardware.h19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) macro
20 #define __io_address(n) ((void __iomem *)IO_ADDRESS(n))
/linux/arch/arm/mach-davinci/
H A Dhardware.h29 #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) macro
/linux/arch/arm/mach-lpc32xx/
H A Dlpc32xx.h711 #define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ macro
714 #define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))