1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
2 /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */
3
4 #ifndef _IONIC_IF_H_
5 #define _IONIC_IF_H_
6
7 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */
8 #define IONIC_DEV_INFO_VERSION 1
9 #define IONIC_IFNAMSIZ 16
10
11 /*
12 * enum ionic_cmd_opcode - Device commands
13 */
14 enum ionic_cmd_opcode {
15 IONIC_CMD_NOP = 0,
16
17 /* Device commands */
18 IONIC_CMD_IDENTIFY = 1,
19 IONIC_CMD_INIT = 2,
20 IONIC_CMD_RESET = 3,
21 IONIC_CMD_GETATTR = 4,
22 IONIC_CMD_SETATTR = 5,
23
24 /* Port commands */
25 IONIC_CMD_PORT_IDENTIFY = 10,
26 IONIC_CMD_PORT_INIT = 11,
27 IONIC_CMD_PORT_RESET = 12,
28 IONIC_CMD_PORT_GETATTR = 13,
29 IONIC_CMD_PORT_SETATTR = 14,
30
31 /* LIF commands */
32 IONIC_CMD_LIF_IDENTIFY = 20,
33 IONIC_CMD_LIF_INIT = 21,
34 IONIC_CMD_LIF_RESET = 22,
35 IONIC_CMD_LIF_GETATTR = 23,
36 IONIC_CMD_LIF_SETATTR = 24,
37 IONIC_CMD_LIF_SETPHC = 25,
38
39 IONIC_CMD_RX_MODE_SET = 30,
40 IONIC_CMD_RX_FILTER_ADD = 31,
41 IONIC_CMD_RX_FILTER_DEL = 32,
42
43 /* Queue commands */
44 IONIC_CMD_Q_IDENTIFY = 39,
45 IONIC_CMD_Q_INIT = 40,
46 IONIC_CMD_Q_CONTROL = 41,
47
48 /* RDMA commands */
49 IONIC_CMD_RDMA_RESET_LIF = 50,
50 IONIC_CMD_RDMA_CREATE_EQ = 51,
51 IONIC_CMD_RDMA_CREATE_CQ = 52,
52 IONIC_CMD_RDMA_CREATE_ADMINQ = 53,
53
54 /* SR/IOV commands */
55 IONIC_CMD_VF_GETATTR = 60,
56 IONIC_CMD_VF_SETATTR = 61,
57 IONIC_CMD_VF_CTRL = 62,
58
59 /* QoS commands */
60 IONIC_CMD_QOS_CLASS_IDENTIFY = 240,
61 IONIC_CMD_QOS_CLASS_INIT = 241,
62 IONIC_CMD_QOS_CLASS_RESET = 242,
63 IONIC_CMD_QOS_CLASS_UPDATE = 243,
64 IONIC_CMD_QOS_CLEAR_STATS = 244,
65 IONIC_CMD_QOS_RESET = 245,
66
67 /* Firmware commands */
68 IONIC_CMD_FW_DOWNLOAD = 252,
69 IONIC_CMD_FW_CONTROL = 253,
70 IONIC_CMD_FW_DOWNLOAD_V1 = 254,
71 IONIC_CMD_FW_CONTROL_V1 = 255,
72 };
73
74 /*
75 * enum ionic_status_code - Device command return codes
76 */
77 enum ionic_status_code {
78 IONIC_RC_SUCCESS = 0, /* Success */
79 IONIC_RC_EVERSION = 1, /* Incorrect version for request */
80 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */
81 IONIC_RC_EIO = 3, /* I/O error */
82 IONIC_RC_EPERM = 4, /* Permission denied */
83 IONIC_RC_EQID = 5, /* Bad qid */
84 IONIC_RC_EQTYPE = 6, /* Bad qtype */
85 IONIC_RC_ENOENT = 7, /* No such element */
86 IONIC_RC_EINTR = 8, /* operation interrupted */
87 IONIC_RC_EAGAIN = 9, /* Try again */
88 IONIC_RC_ENOMEM = 10, /* Out of memory */
89 IONIC_RC_EFAULT = 11, /* Bad address */
90 IONIC_RC_EBUSY = 12, /* Device or resource busy */
91 IONIC_RC_EEXIST = 13, /* object already exists */
92 IONIC_RC_EINVAL = 14, /* Invalid argument */
93 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */
94 IONIC_RC_ERANGE = 16, /* Parameter out of range */
95 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */
96 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */
97 IONIC_RC_ENOSUPP = 19, /* Operation not supported */
98 IONIC_RC_ERROR = 29, /* Generic error */
99 IONIC_RC_ERDMA = 30, /* Generic RDMA error */
100 IONIC_RC_EVFID = 31, /* VF ID does not exist */
101 IONIC_RC_EBAD_FW = 32, /* FW file is invalid or corrupted */
102 };
103
104 enum ionic_notifyq_opcode {
105 IONIC_EVENT_LINK_CHANGE = 1,
106 IONIC_EVENT_RESET = 2,
107 IONIC_EVENT_HEARTBEAT = 3,
108 IONIC_EVENT_LOG = 4,
109 IONIC_EVENT_XCVR = 5,
110 };
111
112 /**
113 * struct ionic_admin_cmd - General admin command format
114 * @opcode: Opcode for the command
115 * @rsvd: reserved byte(s)
116 * @lif_index: LIF index
117 * @cmd_data: Opcode-specific command bytes
118 */
119 struct ionic_admin_cmd {
120 u8 opcode;
121 u8 rsvd;
122 __le16 lif_index;
123 u8 cmd_data[60];
124 };
125
126 /**
127 * struct ionic_admin_comp - General admin command completion format
128 * @status: Status of the command (enum ionic_status_code)
129 * @rsvd: reserved byte(s)
130 * @comp_index: Index in the descriptor ring for which this is the completion
131 * @cmd_data: Command-specific bytes
132 * @color: Color bit (Always 0 for commands issued to the
133 * Device Cmd Registers)
134 */
135 struct ionic_admin_comp {
136 u8 status;
137 u8 rsvd;
138 __le16 comp_index;
139 u8 cmd_data[11];
140 u8 color;
141 #define IONIC_COMP_COLOR_MASK 0x80
142 };
143
color_match(u8 color,u8 done_color)144 static inline u8 color_match(u8 color, u8 done_color)
145 {
146 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color;
147 }
148
149 /**
150 * struct ionic_nop_cmd - NOP command
151 * @opcode: opcode
152 * @rsvd: reserved byte(s)
153 */
154 struct ionic_nop_cmd {
155 u8 opcode;
156 u8 rsvd[63];
157 };
158
159 /**
160 * struct ionic_nop_comp - NOP command completion
161 * @status: Status of the command (enum ionic_status_code)
162 * @rsvd: reserved byte(s)
163 */
164 struct ionic_nop_comp {
165 u8 status;
166 u8 rsvd[15];
167 };
168
169 /**
170 * struct ionic_dev_init_cmd - Device init command
171 * @opcode: opcode
172 * @type: Device type
173 * @rsvd: reserved byte(s)
174 */
175 struct ionic_dev_init_cmd {
176 u8 opcode;
177 u8 type;
178 u8 rsvd[62];
179 };
180
181 /**
182 * struct ionic_dev_init_comp - Device init command completion
183 * @status: Status of the command (enum ionic_status_code)
184 * @rsvd: reserved byte(s)
185 */
186 struct ionic_dev_init_comp {
187 u8 status;
188 u8 rsvd[15];
189 };
190
191 /**
192 * struct ionic_dev_reset_cmd - Device reset command
193 * @opcode: opcode
194 * @rsvd: reserved byte(s)
195 */
196 struct ionic_dev_reset_cmd {
197 u8 opcode;
198 u8 rsvd[63];
199 };
200
201 /**
202 * struct ionic_dev_reset_comp - Reset command completion
203 * @status: Status of the command (enum ionic_status_code)
204 * @rsvd: reserved byte(s)
205 */
206 struct ionic_dev_reset_comp {
207 u8 status;
208 u8 rsvd[15];
209 };
210
211 #define IONIC_IDENTITY_VERSION_1 1
212 #define IONIC_DEV_IDENTITY_VERSION_2 2
213
214 /**
215 * struct ionic_dev_identify_cmd - Driver/device identify command
216 * @opcode: opcode
217 * @ver: Highest version of identify supported by driver
218 * @rsvd: reserved byte(s)
219 */
220 struct ionic_dev_identify_cmd {
221 u8 opcode;
222 u8 ver;
223 u8 rsvd[62];
224 };
225
226 /**
227 * struct ionic_dev_identify_comp - Driver/device identify command completion
228 * @status: Status of the command (enum ionic_status_code)
229 * @ver: Version of identify returned by device
230 * @rsvd: reserved byte(s)
231 */
232 struct ionic_dev_identify_comp {
233 u8 status;
234 u8 ver;
235 u8 rsvd[14];
236 };
237
238 enum ionic_os_type {
239 IONIC_OS_TYPE_LINUX = 1,
240 IONIC_OS_TYPE_WIN = 2,
241 IONIC_OS_TYPE_DPDK = 3,
242 IONIC_OS_TYPE_FREEBSD = 4,
243 IONIC_OS_TYPE_IPXE = 5,
244 IONIC_OS_TYPE_ESXI = 6,
245 };
246
247 /**
248 * union ionic_drv_identity - driver identity information
249 * @os_type: OS type (see enum ionic_os_type)
250 * @os_dist: OS distribution, numeric format
251 * @os_dist_str: OS distribution, string format
252 * @kernel_ver: Kernel version, numeric format
253 * @kernel_ver_str: Kernel version, string format
254 * @driver_ver_str: Driver version, string format
255 * @words: word access to struct contents
256 */
257 union ionic_drv_identity {
258 struct {
259 __le32 os_type;
260 __le32 os_dist;
261 char os_dist_str[128];
262 __le32 kernel_ver;
263 char kernel_ver_str[32];
264 char driver_ver_str[32];
265 };
266 __le32 words[478];
267 };
268
269 /**
270 * enum ionic_dev_capability - Device capabilities
271 * @IONIC_DEV_CAP_VF_CTRL: Device supports VF ctrl operations
272 */
273 enum ionic_dev_capability {
274 IONIC_DEV_CAP_VF_CTRL = BIT(0),
275 };
276
277 /**
278 * union ionic_dev_identity - device identity information
279 * @version: Version of device identify
280 * @type: Identify type (0 for now)
281 * @rsvd: reserved byte(s)
282 * @nports: Number of ports provisioned
283 * @rsvd2: reserved byte(s)
284 * @nlifs: Number of LIFs provisioned
285 * @nintrs: Number of interrupts provisioned
286 * @ndbpgs_per_lif: Number of doorbell pages per LIF
287 * @intr_coal_mult: Interrupt coalescing multiplication factor
288 * Scale user-supplied interrupt coalescing
289 * value in usecs to device units using:
290 * device units = usecs * mult / div
291 * @intr_coal_div: Interrupt coalescing division factor
292 * Scale user-supplied interrupt coalescing
293 * value in usecs to device units using:
294 * device units = usecs * mult / div
295 * @eq_count: Number of shared event queues
296 * @hwstamp_mask: Bitmask for subtraction of hardware tick values.
297 * @hwstamp_mult: Hardware tick to nanosecond multiplier.
298 * @hwstamp_shift: Hardware tick to nanosecond divisor (power of two).
299 * @capabilities: Device capabilities
300 * @words: word access to struct contents
301 */
302 union ionic_dev_identity {
303 struct {
304 u8 version;
305 u8 type;
306 u8 rsvd[2];
307 u8 nports;
308 u8 rsvd2[3];
309 __le32 nlifs;
310 __le32 nintrs;
311 __le32 ndbpgs_per_lif;
312 __le32 intr_coal_mult;
313 __le32 intr_coal_div;
314 __le32 eq_count;
315 __le64 hwstamp_mask;
316 __le32 hwstamp_mult;
317 __le32 hwstamp_shift;
318 __le64 capabilities;
319 };
320 __le32 words[478];
321 };
322
323 enum ionic_lif_type {
324 IONIC_LIF_TYPE_CLASSIC = 0,
325 IONIC_LIF_TYPE_MACVLAN = 1,
326 IONIC_LIF_TYPE_NETQUEUE = 2,
327 };
328
329 /**
330 * struct ionic_lif_identify_cmd - LIF identify command
331 * @opcode: opcode
332 * @type: LIF type (enum ionic_lif_type)
333 * @ver: Version of identify returned by device
334 * @rsvd: reserved byte(s)
335 */
336 struct ionic_lif_identify_cmd {
337 u8 opcode;
338 u8 type;
339 u8 ver;
340 u8 rsvd[61];
341 };
342
343 /**
344 * struct ionic_lif_identify_comp - LIF identify command completion
345 * @status: Status of the command (enum ionic_status_code)
346 * @ver: Version of identify returned by device
347 * @rsvd2: reserved byte(s)
348 */
349 struct ionic_lif_identify_comp {
350 u8 status;
351 u8 ver;
352 u8 rsvd2[14];
353 };
354
355 /**
356 * enum ionic_lif_capability - LIF capabilities
357 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet
358 * @IONIC_LIF_CAP_RDMA: LIF supports RDMA
359 */
360 enum ionic_lif_capability {
361 IONIC_LIF_CAP_ETH = BIT(0),
362 IONIC_LIF_CAP_RDMA = BIT(1),
363 };
364
365 /**
366 * enum ionic_logical_qtype - Logical Queue Types
367 * @IONIC_QTYPE_ADMINQ: Administrative Queue
368 * @IONIC_QTYPE_NOTIFYQ: Notify Queue
369 * @IONIC_QTYPE_RXQ: Receive Queue
370 * @IONIC_QTYPE_TXQ: Transmit Queue
371 * @IONIC_QTYPE_EQ: Event Queue
372 * @IONIC_QTYPE_MAX: Max queue type supported
373 */
374 enum ionic_logical_qtype {
375 IONIC_QTYPE_ADMINQ = 0,
376 IONIC_QTYPE_NOTIFYQ = 1,
377 IONIC_QTYPE_RXQ = 2,
378 IONIC_QTYPE_TXQ = 3,
379 IONIC_QTYPE_EQ = 4,
380 IONIC_QTYPE_MAX = 16,
381 };
382
383 /**
384 * enum ionic_q_feature - Common Features for most queue types
385 *
386 * Common features use bits 0-15. Per-queue-type features use higher bits.
387 *
388 * @IONIC_QIDENT_F_CQ: Queue has completion ring
389 * @IONIC_QIDENT_F_SG: Queue has scatter/gather ring
390 * @IONIC_QIDENT_F_EQ: Queue can use event queue
391 * @IONIC_QIDENT_F_CMB: Queue is in cmb bar
392 * @IONIC_Q_F_2X_DESC: Double main descriptor size
393 * @IONIC_Q_F_2X_CQ_DESC: Double cq descriptor size
394 * @IONIC_Q_F_2X_SG_DESC: Double sg descriptor size
395 * @IONIC_Q_F_4X_DESC: Quadruple main descriptor size
396 * @IONIC_Q_F_4X_CQ_DESC: Quadruple cq descriptor size
397 * @IONIC_Q_F_4X_SG_DESC: Quadruple sg descriptor size
398 */
399 enum ionic_q_feature {
400 IONIC_QIDENT_F_CQ = BIT_ULL(0),
401 IONIC_QIDENT_F_SG = BIT_ULL(1),
402 IONIC_QIDENT_F_EQ = BIT_ULL(2),
403 IONIC_QIDENT_F_CMB = BIT_ULL(3),
404 IONIC_Q_F_2X_DESC = BIT_ULL(4),
405 IONIC_Q_F_2X_CQ_DESC = BIT_ULL(5),
406 IONIC_Q_F_2X_SG_DESC = BIT_ULL(6),
407 IONIC_Q_F_4X_DESC = BIT_ULL(7),
408 IONIC_Q_F_4X_CQ_DESC = BIT_ULL(8),
409 IONIC_Q_F_4X_SG_DESC = BIT_ULL(9),
410 };
411
412 /**
413 * enum ionic_rxq_feature - RXQ-specific Features
414 *
415 * Per-queue-type features use bits 16 and higher.
416 *
417 * @IONIC_RXQ_F_HWSTAMP: Queue supports Hardware Timestamping
418 */
419 enum ionic_rxq_feature {
420 IONIC_RXQ_F_HWSTAMP = BIT_ULL(16),
421 };
422
423 /**
424 * enum ionic_txq_feature - TXQ-specific Features
425 *
426 * Per-queue-type features use bits 16 and higher.
427 *
428 * @IONIC_TXQ_F_HWSTAMP: Queue supports Hardware Timestamping
429 */
430 enum ionic_txq_feature {
431 IONIC_TXQ_F_HWSTAMP = BIT(16),
432 };
433
434 /**
435 * enum ionic_hwstamp_bits - Hardware timestamp decoding bits
436 * @IONIC_HWSTAMP_INVALID: Invalid hardware timestamp value
437 * @IONIC_HWSTAMP_CQ_NEGOFFSET: Timestamp field negative offset
438 * from the base cq descriptor.
439 */
440 enum ionic_hwstamp_bits {
441 IONIC_HWSTAMP_INVALID = ~0ull,
442 IONIC_HWSTAMP_CQ_NEGOFFSET = 8,
443 };
444
445 /**
446 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type
447 * @qtype: Hardware Queue Type
448 * @rsvd: reserved byte(s)
449 * @qid_count: Number of Queue IDs of the logical type
450 * @qid_base: Minimum Queue ID of the logical type
451 */
452 struct ionic_lif_logical_qtype {
453 u8 qtype;
454 u8 rsvd[3];
455 __le32 qid_count;
456 __le32 qid_base;
457 };
458
459 /**
460 * enum ionic_lif_state - LIF state
461 * @IONIC_LIF_DISABLE: LIF disabled
462 * @IONIC_LIF_ENABLE: LIF enabled
463 * @IONIC_LIF_QUIESCE: LIF Quiesced
464 */
465 enum ionic_lif_state {
466 IONIC_LIF_QUIESCE = 0,
467 IONIC_LIF_ENABLE = 1,
468 IONIC_LIF_DISABLE = 2,
469 };
470
471 /**
472 * union ionic_lif_config - LIF configuration
473 * @state: LIF state (enum ionic_lif_state)
474 * @rsvd: reserved byte(s)
475 * @name: LIF name
476 * @mtu: MTU
477 * @mac: Station MAC address
478 * @vlan: Default Vlan ID
479 * @features: Features (enum ionic_eth_hw_features)
480 * @queue_count: Queue counts per queue-type
481 * @words: word access to struct contents
482 */
483 union ionic_lif_config {
484 struct {
485 u8 state;
486 u8 rsvd[3];
487 char name[IONIC_IFNAMSIZ];
488 __le32 mtu;
489 u8 mac[6];
490 __le16 vlan;
491 __le64 features;
492 __le32 queue_count[IONIC_QTYPE_MAX];
493 } __packed;
494 __le32 words[64];
495 };
496
497 /**
498 * struct ionic_lif_identity - LIF identity information (type-specific)
499 *
500 * @capabilities: LIF capabilities
501 *
502 * @eth: Ethernet identify structure
503 * @eth.version: Ethernet identify structure version
504 * @eth.rsvd: reserved byte(s)
505 * @eth.max_ucast_filters: Number of perfect unicast addresses supported
506 * @eth.max_mcast_filters: Number of perfect multicast addresses supported
507 * @eth.min_frame_size: Minimum size of frames to be sent
508 * @eth.max_frame_size: Maximum size of frames to be sent
509 * @eth.rsvd2: reserved byte(s)
510 * @eth.hwstamp_tx_modes: Bitmask of BIT_ULL(enum ionic_txstamp_mode)
511 * @eth.hwstamp_rx_filters: Bitmask of enum ionic_pkt_class
512 * @eth.rsvd3: reserved byte(s)
513 * @eth.config: LIF config struct with features, mtu, mac, q counts
514 *
515 * @rdma: RDMA identify structure
516 * @rdma.version: RDMA version of opcodes and queue descriptors
517 * @rdma.qp_opcodes: Number of RDMA queue pair opcodes supported
518 * @rdma.admin_opcodes: Number of RDMA admin opcodes supported
519 * @rdma.rsvd: reserved byte(s)
520 * @rdma.npts_per_lif: Page table size per LIF
521 * @rdma.nmrs_per_lif: Number of memory regions per LIF
522 * @rdma.nahs_per_lif: Number of address handles per LIF
523 * @rdma.max_stride: Max work request stride
524 * @rdma.cl_stride: Cache line stride
525 * @rdma.pte_stride: Page table entry stride
526 * @rdma.rrq_stride: Remote RQ work request stride
527 * @rdma.rsq_stride: Remote SQ work request stride
528 * @rdma.dcqcn_profiles: Number of DCQCN profiles
529 * @rdma.rsvd_dimensions: reserved byte(s)
530 * @rdma.aq_qtype: RDMA Admin Qtype
531 * @rdma.sq_qtype: RDMA Send Qtype
532 * @rdma.rq_qtype: RDMA Receive Qtype
533 * @rdma.cq_qtype: RDMA Completion Qtype
534 * @rdma.eq_qtype: RDMA Event Qtype
535 * @words: word access to struct contents
536 */
537 union ionic_lif_identity {
538 struct {
539 __le64 capabilities;
540
541 struct {
542 u8 version;
543 u8 rsvd[3];
544 __le32 max_ucast_filters;
545 __le32 max_mcast_filters;
546 __le16 rss_ind_tbl_sz;
547 __le32 min_frame_size;
548 __le32 max_frame_size;
549 u8 rsvd2[2];
550 __le64 hwstamp_tx_modes;
551 __le64 hwstamp_rx_filters;
552 u8 rsvd3[88];
553 union ionic_lif_config config;
554 } __packed eth;
555
556 struct {
557 u8 version;
558 u8 qp_opcodes;
559 u8 admin_opcodes;
560 u8 rsvd;
561 __le32 npts_per_lif;
562 __le32 nmrs_per_lif;
563 __le32 nahs_per_lif;
564 u8 max_stride;
565 u8 cl_stride;
566 u8 pte_stride;
567 u8 rrq_stride;
568 u8 rsq_stride;
569 u8 dcqcn_profiles;
570 u8 rsvd_dimensions[10];
571 struct ionic_lif_logical_qtype aq_qtype;
572 struct ionic_lif_logical_qtype sq_qtype;
573 struct ionic_lif_logical_qtype rq_qtype;
574 struct ionic_lif_logical_qtype cq_qtype;
575 struct ionic_lif_logical_qtype eq_qtype;
576 } __packed rdma;
577 } __packed;
578 __le32 words[478];
579 };
580
581 /**
582 * struct ionic_lif_init_cmd - LIF init command
583 * @opcode: Opcode
584 * @type: LIF type (enum ionic_lif_type)
585 * @index: LIF index
586 * @rsvd: reserved byte(s)
587 * @info_pa: Destination address for LIF info (struct ionic_lif_info)
588 * @rsvd2: reserved byte(s)
589 */
590 struct ionic_lif_init_cmd {
591 u8 opcode;
592 u8 type;
593 __le16 index;
594 __le32 rsvd;
595 __le64 info_pa;
596 u8 rsvd2[48];
597 };
598
599 /**
600 * struct ionic_lif_init_comp - LIF init command completion
601 * @status: Status of the command (enum ionic_status_code)
602 * @rsvd: reserved byte(s)
603 * @hw_index: Hardware index of the initialized LIF
604 * @rsvd2: reserved byte(s)
605 */
606 struct ionic_lif_init_comp {
607 u8 status;
608 u8 rsvd;
609 __le16 hw_index;
610 u8 rsvd2[12];
611 };
612
613 /**
614 * struct ionic_q_identify_cmd - queue identify command
615 * @opcode: opcode
616 * @rsvd: reserved byte(s)
617 * @lif_type: LIF type (enum ionic_lif_type)
618 * @type: Logical queue type (enum ionic_logical_qtype)
619 * @ver: Highest queue type version that the driver supports
620 * @rsvd2: reserved byte(s)
621 */
622 struct ionic_q_identify_cmd {
623 u8 opcode;
624 u8 rsvd;
625 __le16 lif_type;
626 u8 type;
627 u8 ver;
628 u8 rsvd2[58];
629 };
630
631 /**
632 * struct ionic_q_identify_comp - queue identify command completion
633 * @status: Status of the command (enum ionic_status_code)
634 * @rsvd: reserved byte(s)
635 * @comp_index: Index in the descriptor ring for which this is the completion
636 * @ver: Queue type version that can be used with FW
637 * @rsvd2: reserved byte(s)
638 */
639 struct ionic_q_identify_comp {
640 u8 status;
641 u8 rsvd;
642 __le16 comp_index;
643 u8 ver;
644 u8 rsvd2[11];
645 };
646
647 /**
648 * union ionic_q_identity - queue identity information
649 * @version: Queue type version that can be used with FW
650 * @supported: Bitfield of queue versions, first bit = ver 0
651 * @rsvd: reserved byte(s)
652 * @features: Queue features (enum ionic_q_feature, etc)
653 * @desc_sz: Descriptor size
654 * @comp_sz: Completion descriptor size
655 * @sg_desc_sz: Scatter/Gather descriptor size
656 * @max_sg_elems: Maximum number of Scatter/Gather elements
657 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor
658 * @words: word access to struct contents
659 */
660 union ionic_q_identity {
661 struct {
662 u8 version;
663 u8 supported;
664 u8 rsvd[6];
665 __le64 features;
666 __le16 desc_sz;
667 __le16 comp_sz;
668 __le16 sg_desc_sz;
669 __le16 max_sg_elems;
670 __le16 sg_desc_stride;
671 };
672 __le32 words[478];
673 };
674
675 /**
676 * struct ionic_q_init_cmd - Queue init command
677 * @opcode: opcode
678 * @rsvd: reserved byte(s)
679 * @type: Logical queue type
680 * @ver: Queue type version
681 * @rsvd1: reserved byte(s)
682 * @lif_index: LIF index
683 * @index: (LIF, qtype) relative admin queue index
684 * @intr_index: Interrupt control register index, or Event queue index
685 * @pid: Process ID
686 * @flags:
687 * IRQ: Interrupt requested on completion
688 * ENA: Enable the queue. If ENA=0 the queue is initialized
689 * but remains disabled, to be later enabled with the
690 * Queue Enable command. If ENA=1, then queue is
691 * initialized and then enabled.
692 * SG: Enable Scatter-Gather on the queue.
693 * in number of descs. The actual ring size is
694 * (1 << ring_size). For example, to
695 * select a ring size of 64 descriptors write
696 * ring_size = 6. The minimum ring_size value is 2
697 * for a ring size of 4 descriptors. The maximum
698 * ring_size value is 16 for a ring size of 64k
699 * descriptors. Values of ring_size <2 and >16 are
700 * reserved.
701 * EQ: Enable the Event Queue
702 * @cos: Class of service for this queue
703 * @ring_size: Queue ring size, encoded as a log2(size)
704 * @ring_base: Queue ring base address
705 * @cq_ring_base: Completion queue ring base address
706 * @sg_ring_base: Scatter/Gather ring base address
707 * @rsvd2: reserved byte(s)
708 * @features: Mask of queue features to enable, if not in the flags above.
709 */
710 struct ionic_q_init_cmd {
711 u8 opcode;
712 u8 rsvd;
713 __le16 lif_index;
714 u8 type;
715 u8 ver;
716 u8 rsvd1[2];
717 __le32 index;
718 __le16 pid;
719 __le16 intr_index;
720 __le16 flags;
721 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */
722 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */
723 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */
724 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */
725 #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */
726 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */
727 u8 cos;
728 u8 ring_size;
729 __le64 ring_base;
730 __le64 cq_ring_base;
731 __le64 sg_ring_base;
732 u8 rsvd2[12];
733 __le64 features;
734 } __packed;
735
736 /**
737 * struct ionic_q_init_comp - Queue init command completion
738 * @status: Status of the command (enum ionic_status_code)
739 * @rsvd: reserved byte(s)
740 * @comp_index: Index in the descriptor ring for which this is the completion
741 * @hw_index: Hardware Queue ID
742 * @hw_type: Hardware Queue type
743 * @rsvd2: reserved byte(s)
744 * @color: Color
745 */
746 struct ionic_q_init_comp {
747 u8 status;
748 u8 rsvd;
749 __le16 comp_index;
750 __le32 hw_index;
751 u8 hw_type;
752 u8 rsvd2[6];
753 u8 color;
754 };
755
756 /* the device's internal addressing uses up to 52 bits */
757 #define IONIC_ADDR_LEN 52
758 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
759
760 enum ionic_txq_desc_opcode {
761 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0,
762 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1,
763 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2,
764 IONIC_TXQ_DESC_OPCODE_TSO = 3,
765 };
766
767 /**
768 * struct ionic_txq_desc - Ethernet Tx queue descriptor format
769 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*:
770 *
771 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE:
772 * Non-offload send. No segmentation,
773 * fragmentation or checksum calc/insertion is
774 * performed by device; packet is prepared
775 * to send by software stack and requires
776 * no further manipulation from device.
777 *
778 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL:
779 * Offload 16-bit L4 checksum
780 * calculation/insertion. The device will
781 * calculate the L4 checksum value and
782 * insert the result in the packet's L4
783 * header checksum field. The L4 checksum
784 * is calculated starting at @csum_start bytes
785 * into the packet to the end of the packet.
786 * The checksum insertion position is given
787 * in @csum_offset, which is the offset from
788 * @csum_start to the checksum field in the L4
789 * header. This feature is only applicable to
790 * protocols such as TCP, UDP and ICMP where a
791 * standard (i.e. the 'IP-style' checksum)
792 * one's complement 16-bit checksum is used,
793 * using an IP pseudo-header to seed the
794 * calculation. Software will preload the L4
795 * checksum field with the IP pseudo-header
796 * checksum.
797 *
798 * For tunnel encapsulation, @csum_start and
799 * @csum_offset refer to the inner L4
800 * header. Supported tunnels encapsulations
801 * are: IPIP, GRE, and UDP. If the @encap
802 * is clear, no further processing by the
803 * device is required; software will
804 * calculate the outer header checksums. If
805 * the @encap is set, the device will
806 * offload the outer header checksums using
807 * LCO (local checksum offload) (see
808 * Documentation/networking/checksum-offloads.rst
809 * for more info).
810 *
811 * IONIC_TXQ_DESC_OPCODE_CSUM_HW:
812 * Offload 16-bit checksum computation to hardware.
813 * If @csum_l3 is set then the packet's L3 checksum is
814 * updated. Similarly, if @csum_l4 is set the L4
815 * checksum is updated. If @encap is set then encap header
816 * checksums are also updated.
817 *
818 * IONIC_TXQ_DESC_OPCODE_TSO:
819 * Device performs TCP segmentation offload
820 * (TSO). @hdr_len is the number of bytes
821 * to the end of TCP header (the offset to
822 * the TCP payload). @mss is the desired
823 * MSS, the TCP payload length for each
824 * segment. The device will calculate/
825 * insert IP (IPv4 only) and TCP checksums
826 * for each segment. In the first data
827 * buffer containing the header template,
828 * the driver will set IPv4 checksum to 0
829 * and preload TCP checksum with the IP
830 * pseudo header calculated with IP length = 0.
831 *
832 * Supported tunnel encapsulations are IPIP,
833 * layer-3 GRE, and UDP. @hdr_len includes
834 * both outer and inner headers. The driver
835 * will set IPv4 checksum to zero and
836 * preload TCP checksum with IP pseudo
837 * header on the inner header.
838 *
839 * TCP ECN offload is supported. The device
840 * will set CWR flag in the first segment if
841 * CWR is set in the template header, and
842 * clear CWR in remaining segments.
843 * flags:
844 * vlan:
845 * Insert an L2 VLAN header using @vlan_tci
846 * encap:
847 * Calculate encap header checksum
848 * csum_l3:
849 * Compute L3 header checksum
850 * csum_l4:
851 * Compute L4 header checksum
852 * tso_sot:
853 * TSO start
854 * tso_eot:
855 * TSO end
856 * num_sg_elems: Number of scatter-gather elements in SG
857 * descriptor
858 * addr: First data buffer's DMA address
859 * (Subsequent data buffers are on txq_sg_desc)
860 * @len: First data buffer's length, in bytes
861 * @vlan_tci: VLAN tag to insert in the packet (if requested
862 * by @V-bit). Includes .1p and .1q tags
863 * @hword0: half word padding
864 * @hdr_len: Length of packet headers, including
865 * encapsulating outer header, if applicable
866 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and
867 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for
868 * all other modes. For
869 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length
870 * of headers up to inner-most L4 header. For
871 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to
872 * inner-most L4 payload, so inclusive of
873 * inner-most L4 header.
874 * @hword1: half word padding
875 * @mss: Desired MSS value for TSO; only applicable for
876 * IONIC_TXQ_DESC_OPCODE_TSO
877 * @csum_start: Offset from packet to first byte checked in L4 checksum
878 * @csum_offset: Offset from csum_start to L4 checksum field
879 * @hword2: half word padding
880 */
881 struct ionic_txq_desc {
882 __le64 cmd;
883 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf
884 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4
885 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf
886 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0
887 #define IONIC_TXQ_DESC_NSGE_MASK 0xf
888 #define IONIC_TXQ_DESC_NSGE_SHIFT 8
889 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
890 #define IONIC_TXQ_DESC_ADDR_SHIFT 12
891
892 /* common flags */
893 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1
894 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2
895
896 /* flags for csum_hw opcode */
897 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4
898 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8
899
900 /* flags for tso opcode */
901 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4
902 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8
903
904 __le16 len;
905 union {
906 __le16 vlan_tci;
907 __le16 hword0;
908 };
909 union {
910 __le16 csum_start;
911 __le16 hdr_len;
912 __le16 hword1;
913 };
914 union {
915 __le16 csum_offset;
916 __le16 mss;
917 __le16 hword2;
918 };
919 };
920
encode_txq_desc_cmd(u8 opcode,u8 flags,u8 nsge,u64 addr)921 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,
922 u8 nsge, u64 addr)
923 {
924 u64 cmd;
925
926 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT;
927 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT;
928 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT;
929 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT;
930
931 return cmd;
932 };
933
decode_txq_desc_cmd(u64 cmd,u8 * opcode,u8 * flags,u8 * nsge,u64 * addr)934 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,
935 u8 *nsge, u64 *addr)
936 {
937 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK;
938 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK;
939 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK;
940 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK;
941 };
942
943 /**
944 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element
945 * @addr: DMA address of SG element data buffer
946 * @len: Length of SG element data buffer, in bytes
947 * @rsvd: reserved byte(s)
948 */
949 struct ionic_txq_sg_elem {
950 __le64 addr;
951 __le16 len;
952 __le16 rsvd[3];
953 };
954
955 /**
956 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list
957 * @elems: Scatter-gather elements
958 */
959 struct ionic_txq_sg_desc {
960 #define IONIC_TX_MAX_SG_ELEMS 8
961 #define IONIC_TX_SG_DESC_STRIDE 8
962 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS];
963 };
964
965 struct ionic_txq_sg_desc_v1 {
966 #define IONIC_TX_MAX_SG_ELEMS_V1 15
967 #define IONIC_TX_SG_DESC_STRIDE_V1 16
968 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1];
969 };
970
971 /**
972 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor
973 * @status: Status of the command (enum ionic_status_code)
974 * @rsvd: reserved byte(s)
975 * @comp_index: Index in the descriptor ring for which this is the completion
976 * @rsvd2: reserved byte(s)
977 * @color: Color bit
978 */
979 struct ionic_txq_comp {
980 u8 status;
981 u8 rsvd;
982 __le16 comp_index;
983 u8 rsvd2[11];
984 u8 color;
985 };
986
987 enum ionic_rxq_desc_opcode {
988 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0,
989 IONIC_RXQ_DESC_OPCODE_SG = 1,
990 };
991
992 /**
993 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format
994 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*:
995 *
996 * IONIC_RXQ_DESC_OPCODE_SIMPLE:
997 * Receive full packet into data buffer
998 * starting at @addr. Results of
999 * receive, including actual bytes received,
1000 * are recorded in Rx completion descriptor.
1001 *
1002 * @rsvd: reserved byte(s)
1003 * @len: Data buffer's length, in bytes
1004 * @addr: Data buffer's DMA address
1005 */
1006 struct ionic_rxq_desc {
1007 u8 opcode;
1008 u8 rsvd[5];
1009 __le16 len;
1010 __le64 addr;
1011 };
1012
1013 /**
1014 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element
1015 * @addr: DMA address of SG element data buffer
1016 * @len: Length of SG element data buffer, in bytes
1017 * @rsvd: reserved byte(s)
1018 */
1019 struct ionic_rxq_sg_elem {
1020 __le64 addr;
1021 __le16 len;
1022 __le16 rsvd[3];
1023 };
1024
1025 /**
1026 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list
1027 * @elems: Scatter-gather elements
1028 */
1029 struct ionic_rxq_sg_desc {
1030 #define IONIC_RX_MAX_SG_ELEMS 8
1031 #define IONIC_RX_SG_DESC_STRIDE 8
1032 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE];
1033 };
1034
1035 /**
1036 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor
1037 * @status: Status of the command (enum ionic_status_code)
1038 * @num_sg_elems: Number of SG elements used by this descriptor
1039 * @comp_index: Index in the descriptor ring for which this is the completion
1040 * @rss_hash: 32-bit RSS hash
1041 * @csum: 16-bit sum of the packet's L2 payload
1042 * If the packet's L2 payload is odd length, an extra
1043 * zero-value byte is included in the @csum calculation but
1044 * not included in @len.
1045 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is
1046 * set. Includes .1p and .1q tags.
1047 * @len: Received packet length, in bytes. Excludes FCS.
1048 * @csum_calc L2 payload checksum is computed or not
1049 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*:
1050 *
1051 * IONIC_RXQ_COMP_CSUM_F_TCP_OK:
1052 * The TCP checksum calculated by the device
1053 * matched the checksum in the receive packet's
1054 * TCP header.
1055 *
1056 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD:
1057 * The TCP checksum calculated by the device did
1058 * not match the checksum in the receive packet's
1059 * TCP header.
1060 *
1061 * IONIC_RXQ_COMP_CSUM_F_UDP_OK:
1062 * The UDP checksum calculated by the device
1063 * matched the checksum in the receive packet's
1064 * UDP header
1065 *
1066 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD:
1067 * The UDP checksum calculated by the device did
1068 * not match the checksum in the receive packet's
1069 * UDP header.
1070 *
1071 * IONIC_RXQ_COMP_CSUM_F_IP_OK:
1072 * The IPv4 checksum calculated by the device
1073 * matched the checksum in the receive packet's
1074 * first IPv4 header. If the receive packet
1075 * contains both a tunnel IPv4 header and a
1076 * transport IPv4 header, the device validates the
1077 * checksum for the both IPv4 headers.
1078 *
1079 * IONIC_RXQ_COMP_CSUM_F_IP_BAD:
1080 * The IPv4 checksum calculated by the device did
1081 * not match the checksum in the receive packet's
1082 * first IPv4 header. If the receive packet
1083 * contains both a tunnel IPv4 header and a
1084 * transport IPv4 header, the device validates the
1085 * checksum for both IP headers.
1086 *
1087 * IONIC_RXQ_COMP_CSUM_F_VLAN:
1088 * The VLAN header was stripped and placed in @vlan_tci.
1089 *
1090 * IONIC_RXQ_COMP_CSUM_F_CALC:
1091 * The checksum was calculated by the device.
1092 *
1093 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK
1094 */
1095 struct ionic_rxq_comp {
1096 u8 status;
1097 u8 num_sg_elems;
1098 __le16 comp_index;
1099 __le32 rss_hash;
1100 __le16 csum;
1101 __le16 vlan_tci;
1102 __le16 len;
1103 u8 csum_flags;
1104 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01
1105 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02
1106 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04
1107 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08
1108 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10
1109 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20
1110 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40
1111 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80
1112 u8 pkt_type_color;
1113 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f
1114 };
1115
1116 enum ionic_pkt_type {
1117 IONIC_PKT_TYPE_NON_IP = 0x00,
1118 IONIC_PKT_TYPE_IPV4 = 0x01,
1119 IONIC_PKT_TYPE_IPV4_TCP = 0x03,
1120 IONIC_PKT_TYPE_IPV4_UDP = 0x05,
1121 IONIC_PKT_TYPE_IPV6 = 0x08,
1122 IONIC_PKT_TYPE_IPV6_TCP = 0x18,
1123 IONIC_PKT_TYPE_IPV6_UDP = 0x28,
1124 /* below types are only used if encap offloads are enabled on lif */
1125 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40,
1126 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41,
1127 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43,
1128 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45,
1129 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48,
1130 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58,
1131 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68,
1132 };
1133
1134 enum ionic_eth_hw_features {
1135 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0),
1136 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1),
1137 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2),
1138 IONIC_ETH_HW_RX_HASH = BIT(3),
1139 IONIC_ETH_HW_RX_CSUM = BIT(4),
1140 IONIC_ETH_HW_TX_SG = BIT(5),
1141 IONIC_ETH_HW_RX_SG = BIT(6),
1142 IONIC_ETH_HW_TX_CSUM = BIT(7),
1143 IONIC_ETH_HW_TSO = BIT(8),
1144 IONIC_ETH_HW_TSO_IPV6 = BIT(9),
1145 IONIC_ETH_HW_TSO_ECN = BIT(10),
1146 IONIC_ETH_HW_TSO_GRE = BIT(11),
1147 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12),
1148 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13),
1149 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14),
1150 IONIC_ETH_HW_TSO_UDP = BIT(15),
1151 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16),
1152 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17),
1153 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18),
1154 IONIC_ETH_HW_TSO_GENEVE = BIT(19),
1155 IONIC_ETH_HW_TIMESTAMP = BIT(20),
1156 };
1157
1158 /**
1159 * enum ionic_pkt_class - Packet classification mask.
1160 *
1161 * Used with rx steering filter, packets indicated by the mask can be steered
1162 * toward a specific receive queue.
1163 *
1164 * @IONIC_PKT_CLS_NTP_ALL: All NTP packets.
1165 * @IONIC_PKT_CLS_PTP1_SYNC: PTPv1 sync
1166 * @IONIC_PKT_CLS_PTP1_DREQ: PTPv1 delay-request
1167 * @IONIC_PKT_CLS_PTP1_ALL: PTPv1 all packets
1168 * @IONIC_PKT_CLS_PTP2_L4_SYNC: PTPv2-UDP sync
1169 * @IONIC_PKT_CLS_PTP2_L4_DREQ: PTPv2-UDP delay-request
1170 * @IONIC_PKT_CLS_PTP2_L4_ALL: PTPv2-UDP all packets
1171 * @IONIC_PKT_CLS_PTP2_L2_SYNC: PTPv2-ETH sync
1172 * @IONIC_PKT_CLS_PTP2_L2_DREQ: PTPv2-ETH delay-request
1173 * @IONIC_PKT_CLS_PTP2_L2_ALL: PTPv2-ETH all packets
1174 * @IONIC_PKT_CLS_PTP2_SYNC: PTPv2 sync
1175 * @IONIC_PKT_CLS_PTP2_DREQ: PTPv2 delay-request
1176 * @IONIC_PKT_CLS_PTP2_ALL: PTPv2 all packets
1177 * @IONIC_PKT_CLS_PTP_SYNC: PTP sync
1178 * @IONIC_PKT_CLS_PTP_DREQ: PTP delay-request
1179 * @IONIC_PKT_CLS_PTP_ALL: PTP all packets
1180 */
1181 enum ionic_pkt_class {
1182 IONIC_PKT_CLS_NTP_ALL = BIT(0),
1183
1184 IONIC_PKT_CLS_PTP1_SYNC = BIT(1),
1185 IONIC_PKT_CLS_PTP1_DREQ = BIT(2),
1186 IONIC_PKT_CLS_PTP1_ALL = BIT(3) |
1187 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ,
1188
1189 IONIC_PKT_CLS_PTP2_L4_SYNC = BIT(4),
1190 IONIC_PKT_CLS_PTP2_L4_DREQ = BIT(5),
1191 IONIC_PKT_CLS_PTP2_L4_ALL = BIT(6) |
1192 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ,
1193
1194 IONIC_PKT_CLS_PTP2_L2_SYNC = BIT(7),
1195 IONIC_PKT_CLS_PTP2_L2_DREQ = BIT(8),
1196 IONIC_PKT_CLS_PTP2_L2_ALL = BIT(9) |
1197 IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ,
1198
1199 IONIC_PKT_CLS_PTP2_SYNC =
1200 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L2_SYNC,
1201 IONIC_PKT_CLS_PTP2_DREQ =
1202 IONIC_PKT_CLS_PTP2_L4_DREQ | IONIC_PKT_CLS_PTP2_L2_DREQ,
1203 IONIC_PKT_CLS_PTP2_ALL =
1204 IONIC_PKT_CLS_PTP2_L4_ALL | IONIC_PKT_CLS_PTP2_L2_ALL,
1205
1206 IONIC_PKT_CLS_PTP_SYNC =
1207 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP2_SYNC,
1208 IONIC_PKT_CLS_PTP_DREQ =
1209 IONIC_PKT_CLS_PTP1_DREQ | IONIC_PKT_CLS_PTP2_DREQ,
1210 IONIC_PKT_CLS_PTP_ALL =
1211 IONIC_PKT_CLS_PTP1_ALL | IONIC_PKT_CLS_PTP2_ALL,
1212 };
1213
1214 /**
1215 * struct ionic_q_control_cmd - Queue control command
1216 * @opcode: opcode
1217 * @type: Queue type
1218 * @lif_index: LIF index
1219 * @index: Queue index
1220 * @oper: Operation (enum ionic_q_control_oper)
1221 * @rsvd: reserved byte(s)
1222 */
1223 struct ionic_q_control_cmd {
1224 u8 opcode;
1225 u8 type;
1226 __le16 lif_index;
1227 __le32 index;
1228 u8 oper;
1229 u8 rsvd[55];
1230 };
1231
1232 typedef struct ionic_admin_comp ionic_q_control_comp;
1233
1234 enum ionic_q_control_oper {
1235 IONIC_Q_DISABLE = 0,
1236 IONIC_Q_ENABLE = 1,
1237 IONIC_Q_HANG_RESET = 2,
1238 };
1239
1240 /**
1241 * enum ionic_phy_type - Physical connection type
1242 * @IONIC_PHY_TYPE_NONE: No PHY installed
1243 * @IONIC_PHY_TYPE_COPPER: Copper PHY
1244 * @IONIC_PHY_TYPE_FIBER: Fiber PHY
1245 */
1246 enum ionic_phy_type {
1247 IONIC_PHY_TYPE_NONE = 0,
1248 IONIC_PHY_TYPE_COPPER = 1,
1249 IONIC_PHY_TYPE_FIBER = 2,
1250 };
1251
1252 /**
1253 * enum ionic_xcvr_state - Transceiver status
1254 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed
1255 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted
1256 * @IONIC_XCVR_STATE_PENDING: Transceiver pending
1257 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read
1258 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error
1259 */
1260 enum ionic_xcvr_state {
1261 IONIC_XCVR_STATE_REMOVED = 0,
1262 IONIC_XCVR_STATE_INSERTED = 1,
1263 IONIC_XCVR_STATE_PENDING = 2,
1264 IONIC_XCVR_STATE_SPROM_READ = 3,
1265 IONIC_XCVR_STATE_SPROM_READ_ERR = 4,
1266 };
1267
1268 /*
1269 * enum ionic_xcvr_pid - Supported link modes
1270 */
1271 enum ionic_xcvr_pid {
1272 IONIC_XCVR_PID_UNKNOWN = 0,
1273
1274 /* CU */
1275 IONIC_XCVR_PID_QSFP_100G_CR4 = 1,
1276 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2,
1277 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3,
1278 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4,
1279 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5,
1280
1281 /* Fiber */
1282 IONIC_XCVR_PID_QSFP_100G_AOC = 50,
1283 IONIC_XCVR_PID_QSFP_100G_ACC = 51,
1284 IONIC_XCVR_PID_QSFP_100G_SR4 = 52,
1285 IONIC_XCVR_PID_QSFP_100G_LR4 = 53,
1286 IONIC_XCVR_PID_QSFP_100G_ER4 = 54,
1287 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55,
1288 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56,
1289 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57,
1290 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58,
1291 IONIC_XCVR_PID_SFP_25GBASE_SR = 59,
1292 IONIC_XCVR_PID_SFP_25GBASE_LR = 60,
1293 IONIC_XCVR_PID_SFP_25GBASE_ER = 61,
1294 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62,
1295 IONIC_XCVR_PID_SFP_10GBASE_SR = 63,
1296 IONIC_XCVR_PID_SFP_10GBASE_LR = 64,
1297 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65,
1298 IONIC_XCVR_PID_SFP_10GBASE_ER = 66,
1299 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67,
1300 IONIC_XCVR_PID_SFP_10GBASE_CU = 68,
1301 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69,
1302 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70,
1303 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71,
1304 IONIC_XCVR_PID_SFP_10GBASE_T = 72,
1305 IONIC_XCVR_PID_SFP_1000BASE_T = 73,
1306 };
1307
1308 /**
1309 * enum ionic_port_type - Port types
1310 * @IONIC_PORT_TYPE_NONE: Port type not configured
1311 * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband)
1312 * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band)
1313 */
1314 enum ionic_port_type {
1315 IONIC_PORT_TYPE_NONE = 0,
1316 IONIC_PORT_TYPE_ETH = 1,
1317 IONIC_PORT_TYPE_MGMT = 2,
1318 };
1319
1320 /**
1321 * enum ionic_port_admin_state - Port config state
1322 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured
1323 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled
1324 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled
1325 */
1326 enum ionic_port_admin_state {
1327 IONIC_PORT_ADMIN_STATE_NONE = 0,
1328 IONIC_PORT_ADMIN_STATE_DOWN = 1,
1329 IONIC_PORT_ADMIN_STATE_UP = 2,
1330 };
1331
1332 /**
1333 * enum ionic_port_oper_status - Port operational status
1334 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled
1335 * @IONIC_PORT_OPER_STATUS_UP: Port link status up
1336 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down
1337 */
1338 enum ionic_port_oper_status {
1339 IONIC_PORT_OPER_STATUS_NONE = 0,
1340 IONIC_PORT_OPER_STATUS_UP = 1,
1341 IONIC_PORT_OPER_STATUS_DOWN = 2,
1342 };
1343
1344 /**
1345 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes
1346 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled
1347 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC
1348 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC
1349 */
1350 enum ionic_port_fec_type {
1351 IONIC_PORT_FEC_TYPE_NONE = 0,
1352 IONIC_PORT_FEC_TYPE_FC = 1,
1353 IONIC_PORT_FEC_TYPE_RS = 2,
1354 };
1355
1356 /**
1357 * enum ionic_port_pause_type - Ethernet pause (flow control) modes
1358 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause
1359 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause
1360 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control
1361 */
1362 enum ionic_port_pause_type {
1363 IONIC_PORT_PAUSE_TYPE_NONE = 0,
1364 IONIC_PORT_PAUSE_TYPE_LINK = 1,
1365 IONIC_PORT_PAUSE_TYPE_PFC = 2,
1366 };
1367
1368 /**
1369 * enum ionic_port_loopback_mode - Loopback modes
1370 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback
1371 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback
1372 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback
1373 */
1374 enum ionic_port_loopback_mode {
1375 IONIC_PORT_LOOPBACK_MODE_NONE = 0,
1376 IONIC_PORT_LOOPBACK_MODE_MAC = 1,
1377 IONIC_PORT_LOOPBACK_MODE_PHY = 2,
1378 };
1379
1380 /**
1381 * struct ionic_xcvr_status - Transceiver Status information
1382 * @state: Transceiver status (enum ionic_xcvr_state)
1383 * @phy: Physical connection type (enum ionic_phy_type)
1384 * @pid: Transceiver link mode (enum ionic_xcvr_pid)
1385 * @sprom: Transceiver sprom contents
1386 */
1387 struct ionic_xcvr_status {
1388 u8 state;
1389 u8 phy;
1390 __le16 pid;
1391 u8 sprom[256];
1392 };
1393
1394 /**
1395 * union ionic_port_config - Port configuration
1396 * @speed: port speed (in Mbps)
1397 * @mtu: mtu
1398 * @state: port admin state (enum ionic_port_admin_state)
1399 * @an_enable: autoneg enable
1400 * @fec_type: fec type (enum ionic_port_fec_type)
1401 * @pause_type: pause type (enum ionic_port_pause_type)
1402 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode)
1403 * @words: word access to struct contents
1404 */
1405 union ionic_port_config {
1406 struct {
1407 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */
1408 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */
1409 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */
1410 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */
1411 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */
1412 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */
1413 __le32 speed;
1414 __le32 mtu;
1415 u8 state;
1416 u8 an_enable;
1417 u8 fec_type;
1418 #define IONIC_PAUSE_TYPE_MASK 0x0f
1419 #define IONIC_PAUSE_FLAGS_MASK 0xf0
1420 #define IONIC_PAUSE_F_TX 0x10
1421 #define IONIC_PAUSE_F_RX 0x20
1422 u8 pause_type;
1423 u8 loopback_mode;
1424 };
1425 __le32 words[64];
1426 };
1427
1428 /**
1429 * struct ionic_port_status - Port Status information
1430 * @status: link status (enum ionic_port_oper_status)
1431 * @id: port id
1432 * @speed: link speed (in Mbps)
1433 * @link_down_count: number of times link went from up to down
1434 * @fec_type: fec type (enum ionic_port_fec_type)
1435 * @rsvd: reserved byte(s)
1436 * @xcvr: transceiver status
1437 */
1438 struct ionic_port_status {
1439 __le32 id;
1440 __le32 speed;
1441 u8 status;
1442 __le16 link_down_count;
1443 u8 fec_type;
1444 u8 rsvd[48];
1445 struct ionic_xcvr_status xcvr;
1446 } __packed;
1447
1448 /**
1449 * struct ionic_port_identify_cmd - Port identify command
1450 * @opcode: opcode
1451 * @index: port index
1452 * @ver: Highest version of identify supported by driver
1453 * @rsvd: reserved byte(s)
1454 */
1455 struct ionic_port_identify_cmd {
1456 u8 opcode;
1457 u8 index;
1458 u8 ver;
1459 u8 rsvd[61];
1460 };
1461
1462 /**
1463 * struct ionic_port_identify_comp - Port identify command completion
1464 * @status: Status of the command (enum ionic_status_code)
1465 * @ver: Version of identify returned by device
1466 * @rsvd: reserved byte(s)
1467 */
1468 struct ionic_port_identify_comp {
1469 u8 status;
1470 u8 ver;
1471 u8 rsvd[14];
1472 };
1473
1474 /**
1475 * struct ionic_port_init_cmd - Port initialization command
1476 * @opcode: opcode
1477 * @index: port index
1478 * @rsvd: reserved byte(s)
1479 * @info_pa: destination address for port info (struct ionic_port_info)
1480 * @rsvd2: reserved byte(s)
1481 */
1482 struct ionic_port_init_cmd {
1483 u8 opcode;
1484 u8 index;
1485 u8 rsvd[6];
1486 __le64 info_pa;
1487 u8 rsvd2[48];
1488 };
1489
1490 /**
1491 * struct ionic_port_init_comp - Port initialization command completion
1492 * @status: Status of the command (enum ionic_status_code)
1493 * @rsvd: reserved byte(s)
1494 */
1495 struct ionic_port_init_comp {
1496 u8 status;
1497 u8 rsvd[15];
1498 };
1499
1500 /**
1501 * struct ionic_port_reset_cmd - Port reset command
1502 * @opcode: opcode
1503 * @index: port index
1504 * @rsvd: reserved byte(s)
1505 */
1506 struct ionic_port_reset_cmd {
1507 u8 opcode;
1508 u8 index;
1509 u8 rsvd[62];
1510 };
1511
1512 /**
1513 * struct ionic_port_reset_comp - Port reset command completion
1514 * @status: Status of the command (enum ionic_status_code)
1515 * @rsvd: reserved byte(s)
1516 */
1517 struct ionic_port_reset_comp {
1518 u8 status;
1519 u8 rsvd[15];
1520 };
1521
1522 /**
1523 * enum ionic_stats_ctl_cmd - List of commands for stats control
1524 * @IONIC_STATS_CTL_RESET: Reset statistics
1525 */
1526 enum ionic_stats_ctl_cmd {
1527 IONIC_STATS_CTL_RESET = 0,
1528 };
1529
1530 /**
1531 * enum ionic_txstamp_mode - List of TX Timestamping Modes
1532 * @IONIC_TXSTAMP_OFF: Disable TX hardware timetamping.
1533 * @IONIC_TXSTAMP_ON: Enable local TX hardware timetamping.
1534 * @IONIC_TXSTAMP_ONESTEP_SYNC: Modify TX PTP Sync packets.
1535 * @IONIC_TXSTAMP_ONESTEP_P2P: Modify TX PTP Sync and PDelayResp.
1536 */
1537 enum ionic_txstamp_mode {
1538 IONIC_TXSTAMP_OFF = 0,
1539 IONIC_TXSTAMP_ON = 1,
1540 IONIC_TXSTAMP_ONESTEP_SYNC = 2,
1541 IONIC_TXSTAMP_ONESTEP_P2P = 3,
1542 };
1543
1544 /**
1545 * enum ionic_port_attr - List of device attributes
1546 * @IONIC_PORT_ATTR_STATE: Port state attribute
1547 * @IONIC_PORT_ATTR_SPEED: Port speed attribute
1548 * @IONIC_PORT_ATTR_MTU: Port MTU attribute
1549 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotiation attribute
1550 * @IONIC_PORT_ATTR_FEC: Port FEC attribute
1551 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute
1552 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute
1553 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute
1554 */
1555 enum ionic_port_attr {
1556 IONIC_PORT_ATTR_STATE = 0,
1557 IONIC_PORT_ATTR_SPEED = 1,
1558 IONIC_PORT_ATTR_MTU = 2,
1559 IONIC_PORT_ATTR_AUTONEG = 3,
1560 IONIC_PORT_ATTR_FEC = 4,
1561 IONIC_PORT_ATTR_PAUSE = 5,
1562 IONIC_PORT_ATTR_LOOPBACK = 6,
1563 IONIC_PORT_ATTR_STATS_CTRL = 7,
1564 };
1565
1566 /**
1567 * struct ionic_port_setattr_cmd - Set port attributes on the NIC
1568 * @opcode: Opcode
1569 * @index: Port index
1570 * @attr: Attribute type (enum ionic_port_attr)
1571 * @rsvd: reserved byte(s)
1572 * @state: Port state
1573 * @speed: Port speed
1574 * @mtu: Port MTU
1575 * @an_enable: Port autonegotiation setting
1576 * @fec_type: Port FEC type setting
1577 * @pause_type: Port pause type setting
1578 * @loopback_mode: Port loopback mode
1579 * @stats_ctl: Port stats setting
1580 * @rsvd2: reserved byte(s)
1581 */
1582 struct ionic_port_setattr_cmd {
1583 u8 opcode;
1584 u8 index;
1585 u8 attr;
1586 u8 rsvd;
1587 union {
1588 u8 state;
1589 __le32 speed;
1590 __le32 mtu;
1591 u8 an_enable;
1592 u8 fec_type;
1593 u8 pause_type;
1594 u8 loopback_mode;
1595 u8 stats_ctl;
1596 u8 rsvd2[60];
1597 };
1598 };
1599
1600 /**
1601 * struct ionic_port_setattr_comp - Port set attr command completion
1602 * @status: Status of the command (enum ionic_status_code)
1603 * @rsvd: reserved byte(s)
1604 * @color: Color bit
1605 */
1606 struct ionic_port_setattr_comp {
1607 u8 status;
1608 u8 rsvd[14];
1609 u8 color;
1610 };
1611
1612 /**
1613 * struct ionic_port_getattr_cmd - Get port attributes from the NIC
1614 * @opcode: Opcode
1615 * @index: port index
1616 * @attr: Attribute type (enum ionic_port_attr)
1617 * @rsvd: reserved byte(s)
1618 */
1619 struct ionic_port_getattr_cmd {
1620 u8 opcode;
1621 u8 index;
1622 u8 attr;
1623 u8 rsvd[61];
1624 };
1625
1626 /**
1627 * struct ionic_port_getattr_comp - Port get attr command completion
1628 * @status: Status of the command (enum ionic_status_code)
1629 * @rsvd: reserved byte(s)
1630 * @state: Port state
1631 * @speed: Port speed
1632 * @mtu: Port MTU
1633 * @an_enable: Port autonegotiation setting
1634 * @fec_type: Port FEC type setting
1635 * @pause_type: Port pause type setting
1636 * @loopback_mode: Port loopback mode
1637 * @rsvd2: reserved byte(s)
1638 * @color: Color bit
1639 */
1640 struct ionic_port_getattr_comp {
1641 u8 status;
1642 u8 rsvd[3];
1643 union {
1644 u8 state;
1645 __le32 speed;
1646 __le32 mtu;
1647 u8 an_enable;
1648 u8 fec_type;
1649 u8 pause_type;
1650 u8 loopback_mode;
1651 u8 rsvd2[11];
1652 } __packed;
1653 u8 color;
1654 };
1655
1656 /**
1657 * struct ionic_lif_status - LIF status register
1658 * @eid: most recent NotifyQ event id
1659 * @port_num: port the LIF is connected to
1660 * @rsvd: reserved byte(s)
1661 * @link_status: port status (enum ionic_port_oper_status)
1662 * @link_speed: speed of link in Mbps
1663 * @link_down_count: number of times link went from up to down
1664 * @rsvd2: reserved byte(s)
1665 */
1666 struct ionic_lif_status {
1667 __le64 eid;
1668 u8 port_num;
1669 u8 rsvd;
1670 __le16 link_status;
1671 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */
1672 __le16 link_down_count;
1673 u8 rsvd2[46];
1674 };
1675
1676 /**
1677 * struct ionic_lif_reset_cmd - LIF reset command
1678 * @opcode: opcode
1679 * @rsvd: reserved byte(s)
1680 * @index: LIF index
1681 * @rsvd2: reserved byte(s)
1682 */
1683 struct ionic_lif_reset_cmd {
1684 u8 opcode;
1685 u8 rsvd;
1686 __le16 index;
1687 __le32 rsvd2[15];
1688 };
1689
1690 typedef struct ionic_admin_comp ionic_lif_reset_comp;
1691
1692 enum ionic_dev_state {
1693 IONIC_DEV_DISABLE = 0,
1694 IONIC_DEV_ENABLE = 1,
1695 IONIC_DEV_HANG_RESET = 2,
1696 };
1697
1698 /**
1699 * enum ionic_dev_attr - List of device attributes
1700 * @IONIC_DEV_ATTR_STATE: Device state attribute
1701 * @IONIC_DEV_ATTR_NAME: Device name attribute
1702 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes
1703 */
1704 enum ionic_dev_attr {
1705 IONIC_DEV_ATTR_STATE = 0,
1706 IONIC_DEV_ATTR_NAME = 1,
1707 IONIC_DEV_ATTR_FEATURES = 2,
1708 };
1709
1710 /**
1711 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC
1712 * @opcode: Opcode
1713 * @attr: Attribute type (enum ionic_dev_attr)
1714 * @rsvd: reserved byte(s)
1715 * @state: Device state (enum ionic_dev_state)
1716 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated
1717 * @features: Device features
1718 * @rsvd2: reserved byte(s)
1719 */
1720 struct ionic_dev_setattr_cmd {
1721 u8 opcode;
1722 u8 attr;
1723 __le16 rsvd;
1724 union {
1725 u8 state;
1726 char name[IONIC_IFNAMSIZ];
1727 __le64 features;
1728 u8 rsvd2[60];
1729 } __packed;
1730 };
1731
1732 /**
1733 * struct ionic_dev_setattr_comp - Device set attr command completion
1734 * @status: Status of the command (enum ionic_status_code)
1735 * @rsvd: reserved byte(s)
1736 * @features: Device features
1737 * @rsvd2: reserved byte(s)
1738 * @color: Color bit
1739 */
1740 struct ionic_dev_setattr_comp {
1741 u8 status;
1742 u8 rsvd[3];
1743 union {
1744 __le64 features;
1745 u8 rsvd2[11];
1746 } __packed;
1747 u8 color;
1748 };
1749
1750 /**
1751 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC
1752 * @opcode: opcode
1753 * @attr: Attribute type (enum ionic_dev_attr)
1754 * @rsvd: reserved byte(s)
1755 */
1756 struct ionic_dev_getattr_cmd {
1757 u8 opcode;
1758 u8 attr;
1759 u8 rsvd[62];
1760 };
1761
1762 /**
1763 * struct ionic_dev_getattr_comp - Device set attr command completion
1764 * @status: Status of the command (enum ionic_status_code)
1765 * @rsvd: reserved byte(s)
1766 * @features: Device features
1767 * @rsvd2: reserved byte(s)
1768 * @color: Color bit
1769 */
1770 struct ionic_dev_getattr_comp {
1771 u8 status;
1772 u8 rsvd[3];
1773 union {
1774 __le64 features;
1775 u8 rsvd2[11];
1776 } __packed;
1777 u8 color;
1778 };
1779
1780 /*
1781 * RSS parameters
1782 */
1783 #define IONIC_RSS_HASH_KEY_SIZE 40
1784
1785 enum ionic_rss_hash_types {
1786 IONIC_RSS_TYPE_IPV4 = BIT(0),
1787 IONIC_RSS_TYPE_IPV4_TCP = BIT(1),
1788 IONIC_RSS_TYPE_IPV4_UDP = BIT(2),
1789 IONIC_RSS_TYPE_IPV6 = BIT(3),
1790 IONIC_RSS_TYPE_IPV6_TCP = BIT(4),
1791 IONIC_RSS_TYPE_IPV6_UDP = BIT(5),
1792 };
1793
1794 /**
1795 * enum ionic_lif_attr - List of LIF attributes
1796 * @IONIC_LIF_ATTR_STATE: LIF state attribute
1797 * @IONIC_LIF_ATTR_NAME: LIF name attribute
1798 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute
1799 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute
1800 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute
1801 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute
1802 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute
1803 * @IONIC_LIF_ATTR_TXSTAMP: LIF TX timestamping mode
1804 * @IONIC_LIF_ATTR_MAX: maximum attribute value
1805 */
1806 enum ionic_lif_attr {
1807 IONIC_LIF_ATTR_STATE = 0,
1808 IONIC_LIF_ATTR_NAME = 1,
1809 IONIC_LIF_ATTR_MTU = 2,
1810 IONIC_LIF_ATTR_MAC = 3,
1811 IONIC_LIF_ATTR_FEATURES = 4,
1812 IONIC_LIF_ATTR_RSS = 5,
1813 IONIC_LIF_ATTR_STATS_CTRL = 6,
1814 IONIC_LIF_ATTR_TXSTAMP = 7,
1815 IONIC_LIF_ATTR_MAX = 255,
1816 };
1817
1818 /**
1819 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC
1820 * @opcode: Opcode
1821 * @attr: Attribute type (enum ionic_lif_attr)
1822 * @index: LIF index
1823 * @state: LIF state (enum ionic_lif_state)
1824 * @name: The netdev name string, 0 terminated
1825 * @mtu: Mtu
1826 * @mac: Station mac
1827 * @features: Features (enum ionic_eth_hw_features)
1828 * @rss: RSS properties
1829 * @rss.types: The hash types to enable (see rss_hash_types)
1830 * @rss.key: The hash secret key
1831 * @rss.rsvd: reserved byte(s)
1832 * @rss.addr: Address for the indirection table shared memory
1833 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd)
1834 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode)
1835 * @rsvd: reserved byte(s)
1836 */
1837 struct ionic_lif_setattr_cmd {
1838 u8 opcode;
1839 u8 attr;
1840 __le16 index;
1841 union {
1842 u8 state;
1843 char name[IONIC_IFNAMSIZ];
1844 __le32 mtu;
1845 u8 mac[6];
1846 __le64 features;
1847 struct {
1848 __le16 types;
1849 u8 key[IONIC_RSS_HASH_KEY_SIZE];
1850 u8 rsvd[6];
1851 __le64 addr;
1852 } rss;
1853 u8 stats_ctl;
1854 __le16 txstamp_mode;
1855 u8 rsvd[60];
1856 } __packed;
1857 };
1858
1859 /**
1860 * struct ionic_lif_setattr_comp - LIF set attr command completion
1861 * @status: Status of the command (enum ionic_status_code)
1862 * @rsvd: reserved byte(s)
1863 * @comp_index: Index in the descriptor ring for which this is the completion
1864 * @features: features (enum ionic_eth_hw_features)
1865 * @rsvd2: reserved byte(s)
1866 * @color: Color bit
1867 */
1868 struct ionic_lif_setattr_comp {
1869 u8 status;
1870 u8 rsvd;
1871 __le16 comp_index;
1872 union {
1873 __le64 features;
1874 u8 rsvd2[11];
1875 } __packed;
1876 u8 color;
1877 };
1878
1879 /**
1880 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC
1881 * @opcode: Opcode
1882 * @attr: Attribute type (enum ionic_lif_attr)
1883 * @index: LIF index
1884 * @rsvd: reserved byte(s)
1885 */
1886 struct ionic_lif_getattr_cmd {
1887 u8 opcode;
1888 u8 attr;
1889 __le16 index;
1890 u8 rsvd[60];
1891 };
1892
1893 /**
1894 * struct ionic_lif_getattr_comp - LIF get attr command completion
1895 * @status: Status of the command (enum ionic_status_code)
1896 * @rsvd: reserved byte(s)
1897 * @comp_index: Index in the descriptor ring for which this is the completion
1898 * @state: LIF state (enum ionic_lif_state)
1899 * @mtu: Mtu
1900 * @mac: Station mac
1901 * @features: Features (enum ionic_eth_hw_features)
1902 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode)
1903 * @rsvd2: reserved byte(s)
1904 * @color: Color bit
1905 */
1906 struct ionic_lif_getattr_comp {
1907 u8 status;
1908 u8 rsvd;
1909 __le16 comp_index;
1910 union {
1911 u8 state;
1912 __le32 mtu;
1913 u8 mac[6];
1914 __le64 features;
1915 __le16 txstamp_mode;
1916 u8 rsvd2[11];
1917 } __packed;
1918 u8 color;
1919 };
1920
1921 /**
1922 * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock
1923 * @opcode: Opcode
1924 * @rsvd1: reserved byte(s)
1925 * @lif_index: LIF index
1926 * @rsvd2: reserved byte(s)
1927 * @tick: Hardware stamp tick of an instant in time.
1928 * @nsec: Nanosecond stamp of the same instant.
1929 * @frac: Fractional nanoseconds at the same instant.
1930 * @mult: Cycle to nanosecond multiplier.
1931 * @shift: Cycle to nanosecond divisor (power of two).
1932 * @rsvd3: reserved byte(s)
1933 */
1934 struct ionic_lif_setphc_cmd {
1935 u8 opcode;
1936 u8 rsvd1;
1937 __le16 lif_index;
1938 u8 rsvd2[4];
1939 __le64 tick;
1940 __le64 nsec;
1941 __le64 frac;
1942 __le32 mult;
1943 __le32 shift;
1944 u8 rsvd3[24];
1945 };
1946
1947 enum ionic_rx_mode {
1948 IONIC_RX_MODE_F_UNICAST = BIT(0),
1949 IONIC_RX_MODE_F_MULTICAST = BIT(1),
1950 IONIC_RX_MODE_F_BROADCAST = BIT(2),
1951 IONIC_RX_MODE_F_PROMISC = BIT(3),
1952 IONIC_RX_MODE_F_ALLMULTI = BIT(4),
1953 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5),
1954 };
1955
1956 /**
1957 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command
1958 * @opcode: opcode
1959 * @rsvd: reserved byte(s)
1960 * @lif_index: LIF index
1961 * @rx_mode: Rx mode flags:
1962 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets
1963 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets
1964 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets
1965 * IONIC_RX_MODE_F_PROMISC: Accept any packets
1966 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets
1967 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets
1968 * @rsvd2: reserved byte(s)
1969 */
1970 struct ionic_rx_mode_set_cmd {
1971 u8 opcode;
1972 u8 rsvd;
1973 __le16 lif_index;
1974 __le16 rx_mode;
1975 __le16 rsvd2[29];
1976 };
1977
1978 typedef struct ionic_admin_comp ionic_rx_mode_set_comp;
1979
1980 enum ionic_rx_filter_match_type {
1981 IONIC_RX_FILTER_MATCH_VLAN = 0x0,
1982 IONIC_RX_FILTER_MATCH_MAC = 0x1,
1983 IONIC_RX_FILTER_MATCH_MAC_VLAN = 0x2,
1984 IONIC_RX_FILTER_STEER_PKTCLASS = 0x10,
1985 };
1986
1987 /**
1988 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command
1989 * @opcode: opcode
1990 * @qtype: Queue type
1991 * @lif_index: LIF index
1992 * @qid: Queue ID
1993 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx)
1994 * @vlan: VLAN filter
1995 * @vlan.vlan: VLAN ID
1996 * @mac: MAC filter
1997 * @mac.addr: MAC address (network-byte order)
1998 * @mac_vlan: MACVLAN filter
1999 * @mac_vlan.vlan: VLAN ID
2000 * @mac_vlan.addr: MAC address (network-byte order)
2001 * @pkt_class: Packet classification filter
2002 * @rsvd: reserved byte(s)
2003 */
2004 struct ionic_rx_filter_add_cmd {
2005 u8 opcode;
2006 u8 qtype;
2007 __le16 lif_index;
2008 __le32 qid;
2009 __le16 match;
2010 union {
2011 struct {
2012 __le16 vlan;
2013 } vlan;
2014 struct {
2015 u8 addr[6];
2016 } mac;
2017 struct {
2018 __le16 vlan;
2019 u8 addr[6];
2020 } mac_vlan;
2021 __le64 pkt_class;
2022 u8 rsvd[54];
2023 } __packed;
2024 };
2025
2026 /**
2027 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion
2028 * @status: Status of the command (enum ionic_status_code)
2029 * @rsvd: reserved byte(s)
2030 * @comp_index: Index in the descriptor ring for which this is the completion
2031 * @filter_id: Filter ID
2032 * @rsvd2: reserved byte(s)
2033 * @color: Color bit
2034 */
2035 struct ionic_rx_filter_add_comp {
2036 u8 status;
2037 u8 rsvd;
2038 __le16 comp_index;
2039 __le32 filter_id;
2040 u8 rsvd2[7];
2041 u8 color;
2042 };
2043
2044 /**
2045 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command
2046 * @opcode: opcode
2047 * @rsvd: reserved byte(s)
2048 * @lif_index: LIF index
2049 * @filter_id: Filter ID
2050 * @rsvd2: reserved byte(s)
2051 */
2052 struct ionic_rx_filter_del_cmd {
2053 u8 opcode;
2054 u8 rsvd;
2055 __le16 lif_index;
2056 __le32 filter_id;
2057 u8 rsvd2[56];
2058 };
2059
2060 typedef struct ionic_admin_comp ionic_rx_filter_del_comp;
2061
2062 enum ionic_vf_attr {
2063 IONIC_VF_ATTR_SPOOFCHK = 1,
2064 IONIC_VF_ATTR_TRUST = 2,
2065 IONIC_VF_ATTR_MAC = 3,
2066 IONIC_VF_ATTR_LINKSTATE = 4,
2067 IONIC_VF_ATTR_VLAN = 5,
2068 IONIC_VF_ATTR_RATE = 6,
2069 IONIC_VF_ATTR_STATSADDR = 7,
2070 };
2071
2072 /**
2073 * enum ionic_vf_link_status - Virtual Function link status
2074 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink
2075 * @IONIC_VF_LINK_STATUS_UP: Link always up
2076 * @IONIC_VF_LINK_STATUS_DOWN: Link always down
2077 */
2078 enum ionic_vf_link_status {
2079 IONIC_VF_LINK_STATUS_AUTO = 0,
2080 IONIC_VF_LINK_STATUS_UP = 1,
2081 IONIC_VF_LINK_STATUS_DOWN = 2,
2082 };
2083
2084 /**
2085 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC
2086 * @opcode: Opcode
2087 * @attr: Attribute type (enum ionic_vf_attr)
2088 * @vf_index: VF index
2089 * @macaddr: mac address
2090 * @vlanid: vlan ID
2091 * @maxrate: max Tx rate in Mbps
2092 * @spoofchk: enable address spoof checking
2093 * @trust: enable VF trust
2094 * @linkstate: set link up or down
2095 * @stats_pa: set DMA address for VF stats
2096 * @pad: reserved byte(s)
2097 */
2098 struct ionic_vf_setattr_cmd {
2099 u8 opcode;
2100 u8 attr;
2101 __le16 vf_index;
2102 union {
2103 u8 macaddr[6];
2104 __le16 vlanid;
2105 __le32 maxrate;
2106 u8 spoofchk;
2107 u8 trust;
2108 u8 linkstate;
2109 __le64 stats_pa;
2110 u8 pad[60];
2111 } __packed;
2112 };
2113
2114 struct ionic_vf_setattr_comp {
2115 u8 status;
2116 u8 attr;
2117 __le16 vf_index;
2118 __le16 comp_index;
2119 u8 rsvd[9];
2120 u8 color;
2121 };
2122
2123 /**
2124 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC
2125 * @opcode: Opcode
2126 * @attr: Attribute type (enum ionic_vf_attr)
2127 * @vf_index: VF index
2128 * @rsvd: reserved byte(s)
2129 */
2130 struct ionic_vf_getattr_cmd {
2131 u8 opcode;
2132 u8 attr;
2133 __le16 vf_index;
2134 u8 rsvd[60];
2135 };
2136
2137 struct ionic_vf_getattr_comp {
2138 u8 status;
2139 u8 attr;
2140 __le16 vf_index;
2141 union {
2142 u8 macaddr[6];
2143 __le16 vlanid;
2144 __le32 maxrate;
2145 u8 spoofchk;
2146 u8 trust;
2147 u8 linkstate;
2148 __le64 stats_pa;
2149 u8 pad[11];
2150 } __packed;
2151 u8 color;
2152 };
2153
2154 enum ionic_vf_ctrl_opcode {
2155 IONIC_VF_CTRL_START_ALL = 0,
2156 IONIC_VF_CTRL_START = 1,
2157 };
2158
2159 /**
2160 * struct ionic_vf_ctrl_cmd - VF control command
2161 * @opcode: Opcode for the command
2162 * @ctrl_opcode: VF control operation type
2163 * @vf_index: VF Index. It is unused if op START_ALL is used.
2164 */
2165 struct ionic_vf_ctrl_cmd {
2166 u8 opcode;
2167 u8 ctrl_opcode;
2168 __le16 vf_index;
2169 /* private: */
2170 u8 rsvd1[60];
2171 };
2172
2173 /**
2174 * struct ionic_vf_ctrl_comp - VF_CTRL command completion.
2175 * @status: Status of the command (enum ionic_status_code)
2176 */
2177 struct ionic_vf_ctrl_comp {
2178 u8 status;
2179 /* private: */
2180 u8 rsvd[15];
2181 };
2182
2183 /**
2184 * struct ionic_qos_identify_cmd - QoS identify command
2185 * @opcode: opcode
2186 * @ver: Highest version of identify supported by driver
2187 * @rsvd: reserved byte(s)
2188 */
2189 struct ionic_qos_identify_cmd {
2190 u8 opcode;
2191 u8 ver;
2192 u8 rsvd[62];
2193 };
2194
2195 /**
2196 * struct ionic_qos_identify_comp - QoS identify command completion
2197 * @status: Status of the command (enum ionic_status_code)
2198 * @ver: Version of identify returned by device
2199 * @rsvd: reserved byte(s)
2200 */
2201 struct ionic_qos_identify_comp {
2202 u8 status;
2203 u8 ver;
2204 u8 rsvd[14];
2205 };
2206
2207 #define IONIC_QOS_TC_MAX 8
2208 #define IONIC_QOS_ALL_TC 0xFF
2209 /* Capri max supported, should be renamed. */
2210 #define IONIC_QOS_CLASS_MAX 7
2211 #define IONIC_QOS_PCP_MAX 8
2212 #define IONIC_QOS_CLASS_NAME_SZ 32
2213 #define IONIC_QOS_DSCP_MAX 64
2214 #define IONIC_QOS_ALL_PCP 0xFF
2215 #define IONIC_DSCP_BLOCK_SIZE 8
2216
2217 /*
2218 * enum ionic_qos_class
2219 */
2220 enum ionic_qos_class {
2221 IONIC_QOS_CLASS_DEFAULT = 0,
2222 IONIC_QOS_CLASS_USER_DEFINED_1 = 1,
2223 IONIC_QOS_CLASS_USER_DEFINED_2 = 2,
2224 IONIC_QOS_CLASS_USER_DEFINED_3 = 3,
2225 IONIC_QOS_CLASS_USER_DEFINED_4 = 4,
2226 IONIC_QOS_CLASS_USER_DEFINED_5 = 5,
2227 IONIC_QOS_CLASS_USER_DEFINED_6 = 6,
2228 };
2229
2230 /**
2231 * enum ionic_qos_class_type - Traffic classification criteria
2232 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS
2233 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP
2234 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP
2235 */
2236 enum ionic_qos_class_type {
2237 IONIC_QOS_CLASS_TYPE_NONE = 0,
2238 IONIC_QOS_CLASS_TYPE_PCP = 1,
2239 IONIC_QOS_CLASS_TYPE_DSCP = 2,
2240 };
2241
2242 /**
2243 * enum ionic_qos_sched_type - QoS class scheduling type
2244 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority
2245 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin
2246 */
2247 enum ionic_qos_sched_type {
2248 IONIC_QOS_SCHED_TYPE_STRICT = 0,
2249 IONIC_QOS_SCHED_TYPE_DWRR = 1,
2250 };
2251
2252 /**
2253 * union ionic_qos_config - QoS configuration structure
2254 * @flags: Configuration flags
2255 * IONIC_QOS_CONFIG_F_ENABLE enable
2256 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop
2257 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite
2258 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite
2259 * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update
2260 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type)
2261 * @class_type: QoS class type (enum ionic_qos_class_type)
2262 * @pause_type: QoS pause type (enum ionic_qos_pause_type)
2263 * @name: QoS class name
2264 * @mtu: MTU of the class
2265 * @pfc_cos: Priority-Flow Control class of service
2266 * @dwrr_weight: QoS class scheduling weight
2267 * @strict_rlmt: Rate limit for strict priority scheduling
2268 * @rw_dot1q_pcp: Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP)
2269 * @rw_ip_dscp: Rewrite ip dscp to value (valid iff F_RW_IP_DSCP)
2270 * @dot1q_pcp: Dot1q pcp value
2271 * @ndscp: Number of valid dscp values in the ip_dscp field
2272 * @ip_dscp: IP dscp values
2273 * @words: word access to struct contents
2274 */
2275 union ionic_qos_config {
2276 struct {
2277 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0)
2278 #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1)
2279 /* Used to rewrite PCP or DSCP value. */
2280 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2)
2281 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3)
2282 /* Non-disruptive TC update */
2283 #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4)
2284 u8 flags;
2285 u8 sched_type;
2286 u8 class_type;
2287 u8 pause_type;
2288 char name[IONIC_QOS_CLASS_NAME_SZ];
2289 __le32 mtu;
2290 /* flow control */
2291 u8 pfc_cos;
2292 /* scheduler */
2293 union {
2294 u8 dwrr_weight;
2295 __le64 strict_rlmt;
2296 };
2297 /* marking */
2298 /* Used to rewrite PCP or DSCP value. */
2299 union {
2300 u8 rw_dot1q_pcp;
2301 u8 rw_ip_dscp;
2302 };
2303 /* classification */
2304 union {
2305 u8 dot1q_pcp;
2306 struct {
2307 u8 ndscp;
2308 u8 ip_dscp[IONIC_QOS_DSCP_MAX];
2309 };
2310 };
2311 };
2312 __le32 words[64];
2313 };
2314
2315 /**
2316 * union ionic_qos_identity - QoS identity structure
2317 * @version: Version of the identify structure
2318 * @type: QoS system type
2319 * @rsvd: reserved byte(s)
2320 * @config: Current configuration of classes
2321 * @words: word access to struct contents
2322 */
2323 union ionic_qos_identity {
2324 struct {
2325 u8 version;
2326 u8 type;
2327 u8 rsvd[62];
2328 union ionic_qos_config config[IONIC_QOS_CLASS_MAX];
2329 };
2330 __le32 words[478];
2331 };
2332
2333 /**
2334 * struct ionic_qos_init_cmd - QoS config init command
2335 * @opcode: Opcode
2336 * @group: QoS class id
2337 * @rsvd: reserved byte(s)
2338 * @info_pa: destination address for qos info
2339 * @rsvd1: reserved byte(s)
2340 */
2341 struct ionic_qos_init_cmd {
2342 u8 opcode;
2343 u8 group;
2344 u8 rsvd[6];
2345 __le64 info_pa;
2346 u8 rsvd1[48];
2347 };
2348
2349 typedef struct ionic_admin_comp ionic_qos_init_comp;
2350
2351 /**
2352 * struct ionic_qos_reset_cmd - QoS config reset command
2353 * @opcode: Opcode
2354 * @group: QoS class id
2355 * @rsvd: reserved byte(s)
2356 */
2357 struct ionic_qos_reset_cmd {
2358 u8 opcode;
2359 u8 group;
2360 u8 rsvd[62];
2361 };
2362
2363 /**
2364 * struct ionic_qos_clear_stats_cmd - Qos config reset command
2365 * @opcode: Opcode
2366 * @group_bitmap: bitmap of groups to be cleared
2367 * @rsvd: reserved byte(s)
2368 */
2369 struct ionic_qos_clear_stats_cmd {
2370 u8 opcode;
2371 u8 group_bitmap;
2372 u8 rsvd[62];
2373 };
2374
2375 typedef struct ionic_admin_comp ionic_qos_reset_comp;
2376
2377 /**
2378 * struct ionic_fw_download_cmd - Firmware download command
2379 * @opcode: opcode
2380 * @rsvd: reserved byte(s)
2381 * @addr: dma address of the firmware buffer
2382 * @offset: offset of the firmware buffer within the full image
2383 * @length: number of valid bytes in the firmware buffer
2384 */
2385 struct ionic_fw_download_cmd {
2386 u8 opcode;
2387 u8 rsvd[3];
2388 __le32 offset;
2389 __le64 addr;
2390 __le32 length;
2391 };
2392
2393 typedef struct ionic_admin_comp ionic_fw_download_comp;
2394
2395 /**
2396 * enum ionic_fw_control_oper - FW control operations
2397 * @IONIC_FW_RESET: Reset firmware
2398 * @IONIC_FW_INSTALL: Install firmware
2399 * @IONIC_FW_ACTIVATE: Activate firmware
2400 * @IONIC_FW_INSTALL_ASYNC: Install firmware asynchronously
2401 * @IONIC_FW_INSTALL_STATUS: Firmware installation status
2402 * @IONIC_FW_ACTIVATE_ASYNC: Activate firmware asynchronously
2403 * @IONIC_FW_ACTIVATE_STATUS: Firmware activate status
2404 * @IONIC_FW_UPDATE_CLEANUP: Clean up after an interrupted fw update
2405 */
2406 enum ionic_fw_control_oper {
2407 IONIC_FW_RESET = 0,
2408 IONIC_FW_INSTALL = 1,
2409 IONIC_FW_ACTIVATE = 2,
2410 IONIC_FW_INSTALL_ASYNC = 3,
2411 IONIC_FW_INSTALL_STATUS = 4,
2412 IONIC_FW_ACTIVATE_ASYNC = 5,
2413 IONIC_FW_ACTIVATE_STATUS = 6,
2414 IONIC_FW_UPDATE_CLEANUP = 7,
2415 };
2416
2417 /**
2418 * struct ionic_fw_control_cmd - Firmware control command
2419 * @opcode: opcode
2420 * @rsvd: reserved byte(s)
2421 * @oper: firmware control operation (enum ionic_fw_control_oper)
2422 * @slot: slot to activate
2423 * @rsvd1: reserved byte(s)
2424 */
2425 struct ionic_fw_control_cmd {
2426 u8 opcode;
2427 u8 rsvd[3];
2428 u8 oper;
2429 u8 slot;
2430 u8 rsvd1[58];
2431 };
2432
2433 /**
2434 * struct ionic_fw_control_comp - Firmware control copletion
2435 * @status: Status of the command (enum ionic_status_code)
2436 * @rsvd: reserved byte(s)
2437 * @comp_index: Index in the descriptor ring for which this is the completion
2438 * @slot: Slot where the firmware was installed
2439 * @rsvd1: reserved byte(s)
2440 * @color: Color bit
2441 */
2442 struct ionic_fw_control_comp {
2443 u8 status;
2444 u8 rsvd;
2445 __le16 comp_index;
2446 u8 slot;
2447 u8 rsvd1[10];
2448 u8 color;
2449 };
2450
2451 /******************************************************************
2452 ******************* RDMA Commands ********************************
2453 ******************************************************************/
2454
2455 /**
2456 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd
2457 * @opcode: opcode
2458 * @rsvd: reserved byte(s)
2459 * @lif_index: LIF index
2460 * @rsvd2: reserved byte(s)
2461 *
2462 * There is no RDMA specific dev command completion struct. Completion uses
2463 * the common struct ionic_admin_comp. Only the status is indicated.
2464 * Nonzero status means the LIF does not support RDMA.
2465 **/
2466 struct ionic_rdma_reset_cmd {
2467 u8 opcode;
2468 u8 rsvd;
2469 __le16 lif_index;
2470 u8 rsvd2[60];
2471 };
2472
2473 /**
2474 * struct ionic_rdma_queue_cmd - Create RDMA Queue command
2475 * @opcode: opcode, 52, 53
2476 * @rsvd: reserved byte(s)
2477 * @lif_index: LIF index
2478 * @qid_ver: (qid | (RDMA version << 24))
2479 * @cid: intr, eq_id, or cq_id
2480 * @dbid: doorbell page id
2481 * @depth_log2: log base two of queue depth
2482 * @stride_log2: log base two of queue stride
2483 * @dma_addr: address of the queue memory
2484 * @rsvd2: reserved byte(s)
2485 *
2486 * The same command struct is used to create an RDMA event queue, completion
2487 * queue, or RDMA admin queue. The cid is an interrupt number for an event
2488 * queue, an event queue id for a completion queue, or a completion queue id
2489 * for an RDMA admin queue.
2490 *
2491 * The queue created via a dev command must be contiguous in dma space.
2492 *
2493 * The dev commands are intended only to be used during driver initialization,
2494 * to create queues supporting the RDMA admin queue. Other queues, and other
2495 * types of RDMA resources like memory regions, will be created and registered
2496 * via the RDMA admin queue, and will support a more complete interface
2497 * providing scatter gather lists for larger, scattered queue buffers and
2498 * memory registration.
2499 *
2500 * There is no RDMA specific dev command completion struct. Completion uses
2501 * the common struct ionic_admin_comp. Only the status is indicated.
2502 **/
2503 struct ionic_rdma_queue_cmd {
2504 u8 opcode;
2505 u8 rsvd;
2506 __le16 lif_index;
2507 __le32 qid_ver;
2508 __le32 cid;
2509 __le16 dbid;
2510 u8 depth_log2;
2511 u8 stride_log2;
2512 __le64 dma_addr;
2513 u8 rsvd2[40];
2514 };
2515
2516 /******************************************************************
2517 ******************* Notify Events ********************************
2518 ******************************************************************/
2519
2520 /**
2521 * struct ionic_notifyq_event - Generic event reporting structure
2522 * @eid: event number
2523 * @ecode: event code
2524 * @data: unspecified data about the event
2525 *
2526 * This is the generic event report struct from which the other
2527 * actual events will be formed.
2528 */
2529 struct ionic_notifyq_event {
2530 __le64 eid;
2531 __le16 ecode;
2532 u8 data[54];
2533 };
2534
2535 /**
2536 * struct ionic_link_change_event - Link change event notification
2537 * @eid: event number
2538 * @ecode: event code = IONIC_EVENT_LINK_CHANGE
2539 * @link_status: link up/down, with error bits (enum ionic_port_status)
2540 * @link_speed: speed of the network link
2541 * @rsvd: reserved byte(s)
2542 *
2543 * Sent when the network link state changes between UP and DOWN
2544 */
2545 struct ionic_link_change_event {
2546 __le64 eid;
2547 __le16 ecode;
2548 __le16 link_status;
2549 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */
2550 u8 rsvd[48];
2551 };
2552
2553 /**
2554 * struct ionic_reset_event - Reset event notification
2555 * @eid: event number
2556 * @ecode: event code = IONIC_EVENT_RESET
2557 * @reset_code: reset type
2558 * @state: 0=pending, 1=complete, 2=error
2559 * @rsvd: reserved byte(s)
2560 *
2561 * Sent when the NIC or some subsystem is going to be or
2562 * has been reset.
2563 */
2564 struct ionic_reset_event {
2565 __le64 eid;
2566 __le16 ecode;
2567 u8 reset_code;
2568 u8 state;
2569 u8 rsvd[52];
2570 };
2571
2572 /**
2573 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health
2574 * @eid: event number
2575 * @ecode: event code = IONIC_EVENT_HEARTBEAT
2576 * @rsvd: reserved byte(s)
2577 */
2578 struct ionic_heartbeat_event {
2579 __le64 eid;
2580 __le16 ecode;
2581 u8 rsvd[54];
2582 };
2583
2584 /**
2585 * struct ionic_log_event - Sent to notify the driver of an internal error
2586 * @eid: event number
2587 * @ecode: event code = IONIC_EVENT_LOG
2588 * @data: log data
2589 */
2590 struct ionic_log_event {
2591 __le64 eid;
2592 __le16 ecode;
2593 u8 data[54];
2594 };
2595
2596 /**
2597 * struct ionic_xcvr_event - Transceiver change event
2598 * @eid: event number
2599 * @ecode: event code = IONIC_EVENT_XCVR
2600 * @rsvd: reserved byte(s)
2601 */
2602 struct ionic_xcvr_event {
2603 __le64 eid;
2604 __le16 ecode;
2605 u8 rsvd[54];
2606 };
2607
2608 /*
2609 * struct ionic_port_stats - Port statistics structure
2610 */
2611 struct ionic_port_stats {
2612 __le64 frames_rx_ok;
2613 __le64 frames_rx_all;
2614 __le64 frames_rx_bad_fcs;
2615 __le64 frames_rx_bad_all;
2616 __le64 octets_rx_ok;
2617 __le64 octets_rx_all;
2618 __le64 frames_rx_unicast;
2619 __le64 frames_rx_multicast;
2620 __le64 frames_rx_broadcast;
2621 __le64 frames_rx_pause;
2622 __le64 frames_rx_bad_length;
2623 __le64 frames_rx_undersized;
2624 __le64 frames_rx_oversized;
2625 __le64 frames_rx_fragments;
2626 __le64 frames_rx_jabber;
2627 __le64 frames_rx_pripause;
2628 __le64 frames_rx_stomped_crc;
2629 __le64 frames_rx_too_long;
2630 __le64 frames_rx_vlan_good;
2631 __le64 frames_rx_dropped;
2632 __le64 frames_rx_less_than_64b;
2633 __le64 frames_rx_64b;
2634 __le64 frames_rx_65b_127b;
2635 __le64 frames_rx_128b_255b;
2636 __le64 frames_rx_256b_511b;
2637 __le64 frames_rx_512b_1023b;
2638 __le64 frames_rx_1024b_1518b;
2639 __le64 frames_rx_1519b_2047b;
2640 __le64 frames_rx_2048b_4095b;
2641 __le64 frames_rx_4096b_8191b;
2642 __le64 frames_rx_8192b_9215b;
2643 __le64 frames_rx_other;
2644 __le64 frames_tx_ok;
2645 __le64 frames_tx_all;
2646 __le64 frames_tx_bad;
2647 __le64 octets_tx_ok;
2648 __le64 octets_tx_total;
2649 __le64 frames_tx_unicast;
2650 __le64 frames_tx_multicast;
2651 __le64 frames_tx_broadcast;
2652 __le64 frames_tx_pause;
2653 __le64 frames_tx_pripause;
2654 __le64 frames_tx_vlan;
2655 __le64 frames_tx_less_than_64b;
2656 __le64 frames_tx_64b;
2657 __le64 frames_tx_65b_127b;
2658 __le64 frames_tx_128b_255b;
2659 __le64 frames_tx_256b_511b;
2660 __le64 frames_tx_512b_1023b;
2661 __le64 frames_tx_1024b_1518b;
2662 __le64 frames_tx_1519b_2047b;
2663 __le64 frames_tx_2048b_4095b;
2664 __le64 frames_tx_4096b_8191b;
2665 __le64 frames_tx_8192b_9215b;
2666 __le64 frames_tx_other;
2667 __le64 frames_tx_pri_0;
2668 __le64 frames_tx_pri_1;
2669 __le64 frames_tx_pri_2;
2670 __le64 frames_tx_pri_3;
2671 __le64 frames_tx_pri_4;
2672 __le64 frames_tx_pri_5;
2673 __le64 frames_tx_pri_6;
2674 __le64 frames_tx_pri_7;
2675 __le64 frames_rx_pri_0;
2676 __le64 frames_rx_pri_1;
2677 __le64 frames_rx_pri_2;
2678 __le64 frames_rx_pri_3;
2679 __le64 frames_rx_pri_4;
2680 __le64 frames_rx_pri_5;
2681 __le64 frames_rx_pri_6;
2682 __le64 frames_rx_pri_7;
2683 __le64 tx_pripause_0_1us_count;
2684 __le64 tx_pripause_1_1us_count;
2685 __le64 tx_pripause_2_1us_count;
2686 __le64 tx_pripause_3_1us_count;
2687 __le64 tx_pripause_4_1us_count;
2688 __le64 tx_pripause_5_1us_count;
2689 __le64 tx_pripause_6_1us_count;
2690 __le64 tx_pripause_7_1us_count;
2691 __le64 rx_pripause_0_1us_count;
2692 __le64 rx_pripause_1_1us_count;
2693 __le64 rx_pripause_2_1us_count;
2694 __le64 rx_pripause_3_1us_count;
2695 __le64 rx_pripause_4_1us_count;
2696 __le64 rx_pripause_5_1us_count;
2697 __le64 rx_pripause_6_1us_count;
2698 __le64 rx_pripause_7_1us_count;
2699 __le64 rx_pause_1us_count;
2700 __le64 frames_tx_truncated;
2701 };
2702
2703 struct ionic_mgmt_port_stats {
2704 __le64 frames_rx_ok;
2705 __le64 frames_rx_all;
2706 __le64 frames_rx_bad_fcs;
2707 __le64 frames_rx_bad_all;
2708 __le64 octets_rx_ok;
2709 __le64 octets_rx_all;
2710 __le64 frames_rx_unicast;
2711 __le64 frames_rx_multicast;
2712 __le64 frames_rx_broadcast;
2713 __le64 frames_rx_pause;
2714 __le64 frames_rx_bad_length;
2715 __le64 frames_rx_undersized;
2716 __le64 frames_rx_oversized;
2717 __le64 frames_rx_fragments;
2718 __le64 frames_rx_jabber;
2719 __le64 frames_rx_64b;
2720 __le64 frames_rx_65b_127b;
2721 __le64 frames_rx_128b_255b;
2722 __le64 frames_rx_256b_511b;
2723 __le64 frames_rx_512b_1023b;
2724 __le64 frames_rx_1024b_1518b;
2725 __le64 frames_rx_gt_1518b;
2726 __le64 frames_rx_fifo_full;
2727 __le64 frames_tx_ok;
2728 __le64 frames_tx_all;
2729 __le64 frames_tx_bad;
2730 __le64 octets_tx_ok;
2731 __le64 octets_tx_total;
2732 __le64 frames_tx_unicast;
2733 __le64 frames_tx_multicast;
2734 __le64 frames_tx_broadcast;
2735 __le64 frames_tx_pause;
2736 };
2737
2738 enum ionic_pb_buffer_drop_stats {
2739 IONIC_BUFFER_INTRINSIC_DROP = 0,
2740 IONIC_BUFFER_DISCARDED,
2741 IONIC_BUFFER_ADMITTED,
2742 IONIC_BUFFER_OUT_OF_CELLS_DROP,
2743 IONIC_BUFFER_OUT_OF_CELLS_DROP_2,
2744 IONIC_BUFFER_OUT_OF_CREDIT_DROP,
2745 IONIC_BUFFER_TRUNCATION_DROP,
2746 IONIC_BUFFER_PORT_DISABLED_DROP,
2747 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP,
2748 IONIC_BUFFER_SPAN_TAIL_DROP,
2749 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP,
2750 IONIC_BUFFER_ENQUEUE_ERROR_DROP,
2751 IONIC_BUFFER_INVALID_PORT_DROP,
2752 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP,
2753 IONIC_BUFFER_DROP_MAX,
2754 };
2755
2756 enum ionic_oflow_drop_stats {
2757 IONIC_OFLOW_OCCUPANCY_DROP,
2758 IONIC_OFLOW_EMERGENCY_STOP_DROP,
2759 IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP,
2760 IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP,
2761 IONIC_OFLOW_WRITE_BUFFER_FULL_DROP,
2762 IONIC_OFLOW_CONTROL_FIFO_FULL_DROP,
2763 IONIC_OFLOW_DROP_MAX,
2764 };
2765
2766 /* struct ionic_port_pb_stats - packet buffers system stats
2767 * uses ionic_pb_buffer_drop_stats for drop_counts[]
2768 */
2769 struct ionic_port_pb_stats {
2770 __le64 sop_count_in;
2771 __le64 eop_count_in;
2772 __le64 sop_count_out;
2773 __le64 eop_count_out;
2774 __le64 drop_counts[IONIC_BUFFER_DROP_MAX];
2775 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2776 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX];
2777 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX];
2778 __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX];
2779 __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX];
2780 __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX];
2781 __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX];
2782 __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX];
2783 __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX];
2784 __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX];
2785 __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2786 };
2787
2788 /**
2789 * struct ionic_port_identity - port identity structure
2790 * @version: identity structure version
2791 * @type: type of port (enum ionic_port_type)
2792 * @num_lanes: number of lanes for the port
2793 * @autoneg: autoneg supported
2794 * @min_frame_size: minimum frame size supported
2795 * @max_frame_size: maximum frame size supported
2796 * @fec_type: supported fec types
2797 * @pause_type: supported pause types
2798 * @loopback_mode: supported loopback mode
2799 * @speeds: supported speeds
2800 * @rsvd2: reserved byte(s)
2801 * @config: current port configuration
2802 * @words: word access to struct contents
2803 */
2804 union ionic_port_identity {
2805 struct {
2806 u8 version;
2807 u8 type;
2808 u8 num_lanes;
2809 u8 autoneg;
2810 __le32 min_frame_size;
2811 __le32 max_frame_size;
2812 u8 fec_type[4];
2813 u8 pause_type[2];
2814 u8 loopback_mode[2];
2815 __le32 speeds[16];
2816 u8 rsvd2[44];
2817 union ionic_port_config config;
2818 };
2819 __le32 words[478];
2820 };
2821
2822 /**
2823 * struct ionic_port_info - port info structure
2824 * @config: Port configuration data
2825 * @status: Port status data
2826 * @stats: Port statistics data
2827 * @mgmt_stats: Port management statistics data
2828 * @rsvd: reserved byte(s)
2829 * @pb_stats: uplink pb drop stats
2830 */
2831 struct ionic_port_info {
2832 union ionic_port_config config;
2833 struct ionic_port_status status;
2834 union {
2835 struct ionic_port_stats stats;
2836 struct ionic_mgmt_port_stats mgmt_stats;
2837 };
2838 /* room for pb_stats to start at 2k offset */
2839 u8 rsvd[760];
2840 struct ionic_port_pb_stats pb_stats;
2841 };
2842
2843 /*
2844 * struct ionic_lif_stats - LIF statistics structure
2845 */
2846 struct ionic_lif_stats {
2847 /* RX */
2848 __le64 rx_ucast_bytes;
2849 __le64 rx_ucast_packets;
2850 __le64 rx_mcast_bytes;
2851 __le64 rx_mcast_packets;
2852 __le64 rx_bcast_bytes;
2853 __le64 rx_bcast_packets;
2854 __le64 rsvd0;
2855 __le64 rsvd1;
2856 /* RX drops */
2857 __le64 rx_ucast_drop_bytes;
2858 __le64 rx_ucast_drop_packets;
2859 __le64 rx_mcast_drop_bytes;
2860 __le64 rx_mcast_drop_packets;
2861 __le64 rx_bcast_drop_bytes;
2862 __le64 rx_bcast_drop_packets;
2863 __le64 rx_dma_error;
2864 __le64 rsvd2;
2865 /* TX */
2866 __le64 tx_ucast_bytes;
2867 __le64 tx_ucast_packets;
2868 __le64 tx_mcast_bytes;
2869 __le64 tx_mcast_packets;
2870 __le64 tx_bcast_bytes;
2871 __le64 tx_bcast_packets;
2872 __le64 rsvd3;
2873 __le64 rsvd4;
2874 /* TX drops */
2875 __le64 tx_ucast_drop_bytes;
2876 __le64 tx_ucast_drop_packets;
2877 __le64 tx_mcast_drop_bytes;
2878 __le64 tx_mcast_drop_packets;
2879 __le64 tx_bcast_drop_bytes;
2880 __le64 tx_bcast_drop_packets;
2881 __le64 tx_dma_error;
2882 __le64 rsvd5;
2883 /* Rx Queue/Ring drops */
2884 __le64 rx_queue_disabled;
2885 __le64 rx_queue_empty;
2886 __le64 rx_queue_error;
2887 __le64 rx_desc_fetch_error;
2888 __le64 rx_desc_data_error;
2889 __le64 rsvd6;
2890 __le64 rsvd7;
2891 __le64 rsvd8;
2892 /* Tx Queue/Ring drops */
2893 __le64 tx_queue_disabled;
2894 __le64 tx_queue_error;
2895 __le64 tx_desc_fetch_error;
2896 __le64 tx_desc_data_error;
2897 __le64 tx_queue_empty;
2898 __le64 rsvd10;
2899 __le64 rsvd11;
2900 __le64 rsvd12;
2901
2902 /* RDMA/ROCE TX */
2903 __le64 tx_rdma_ucast_bytes;
2904 __le64 tx_rdma_ucast_packets;
2905 __le64 tx_rdma_mcast_bytes;
2906 __le64 tx_rdma_mcast_packets;
2907 __le64 tx_rdma_cnp_packets;
2908 __le64 rsvd13;
2909 __le64 rsvd14;
2910 __le64 rsvd15;
2911
2912 /* RDMA/ROCE RX */
2913 __le64 rx_rdma_ucast_bytes;
2914 __le64 rx_rdma_ucast_packets;
2915 __le64 rx_rdma_mcast_bytes;
2916 __le64 rx_rdma_mcast_packets;
2917 __le64 rx_rdma_cnp_packets;
2918 __le64 rx_rdma_ecn_packets;
2919 __le64 rsvd16;
2920 __le64 rsvd17;
2921
2922 __le64 rsvd18;
2923 __le64 rsvd19;
2924 __le64 rsvd20;
2925 __le64 rsvd21;
2926 __le64 rsvd22;
2927 __le64 rsvd23;
2928 __le64 rsvd24;
2929 __le64 rsvd25;
2930
2931 __le64 rsvd26;
2932 __le64 rsvd27;
2933 __le64 rsvd28;
2934 __le64 rsvd29;
2935 __le64 rsvd30;
2936 __le64 rsvd31;
2937 __le64 rsvd32;
2938 __le64 rsvd33;
2939
2940 __le64 rsvd34;
2941 __le64 rsvd35;
2942 __le64 rsvd36;
2943 __le64 rsvd37;
2944 __le64 rsvd38;
2945 __le64 rsvd39;
2946 __le64 rsvd40;
2947 __le64 rsvd41;
2948
2949 __le64 rsvd42;
2950 __le64 rsvd43;
2951 __le64 rsvd44;
2952 __le64 rsvd45;
2953 __le64 rsvd46;
2954 __le64 rsvd47;
2955 __le64 rsvd48;
2956 __le64 rsvd49;
2957
2958 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */
2959 __le64 rdma_req_rx_pkt_seq_err;
2960 __le64 rdma_req_rx_rnr_retry_err;
2961 __le64 rdma_req_rx_remote_access_err;
2962 __le64 rdma_req_rx_remote_inv_req_err;
2963 __le64 rdma_req_rx_remote_oper_err;
2964 __le64 rdma_req_rx_implied_nak_seq_err;
2965 __le64 rdma_req_rx_cqe_err;
2966 __le64 rdma_req_rx_cqe_flush_err;
2967
2968 __le64 rdma_req_rx_dup_responses;
2969 __le64 rdma_req_rx_invalid_packets;
2970 __le64 rdma_req_tx_local_access_err;
2971 __le64 rdma_req_tx_local_oper_err;
2972 __le64 rdma_req_tx_memory_mgmt_err;
2973 __le64 rsvd52;
2974 __le64 rsvd53;
2975 __le64 rsvd54;
2976
2977 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */
2978 __le64 rdma_resp_rx_dup_requests;
2979 __le64 rdma_resp_rx_out_of_buffer;
2980 __le64 rdma_resp_rx_out_of_seq_pkts;
2981 __le64 rdma_resp_rx_cqe_err;
2982 __le64 rdma_resp_rx_cqe_flush_err;
2983 __le64 rdma_resp_rx_local_len_err;
2984 __le64 rdma_resp_rx_inv_request_err;
2985 __le64 rdma_resp_rx_local_qp_oper_err;
2986
2987 __le64 rdma_resp_rx_out_of_atomic_resource;
2988 __le64 rdma_resp_tx_pkt_seq_err;
2989 __le64 rdma_resp_tx_remote_inv_req_err;
2990 __le64 rdma_resp_tx_remote_access_err;
2991 __le64 rdma_resp_tx_remote_oper_err;
2992 __le64 rdma_resp_tx_rnr_retry_err;
2993 __le64 rsvd57;
2994 __le64 rsvd58;
2995 };
2996
2997 /**
2998 * struct ionic_lif_info - LIF info structure
2999 * @config: LIF configuration structure
3000 * @status: LIF status structure
3001 * @stats: LIF statistics structure
3002 */
3003 struct ionic_lif_info {
3004 union ionic_lif_config config;
3005 struct ionic_lif_status status;
3006 struct ionic_lif_stats stats;
3007 };
3008
3009 union ionic_dev_cmd {
3010 u32 words[16];
3011 struct ionic_admin_cmd cmd;
3012 struct ionic_nop_cmd nop;
3013
3014 struct ionic_dev_identify_cmd identify;
3015 struct ionic_dev_init_cmd init;
3016 struct ionic_dev_reset_cmd reset;
3017 struct ionic_dev_getattr_cmd getattr;
3018 struct ionic_dev_setattr_cmd setattr;
3019
3020 struct ionic_port_identify_cmd port_identify;
3021 struct ionic_port_init_cmd port_init;
3022 struct ionic_port_reset_cmd port_reset;
3023 struct ionic_port_getattr_cmd port_getattr;
3024 struct ionic_port_setattr_cmd port_setattr;
3025
3026 struct ionic_vf_setattr_cmd vf_setattr;
3027 struct ionic_vf_getattr_cmd vf_getattr;
3028 struct ionic_vf_ctrl_cmd vf_ctrl;
3029
3030 struct ionic_lif_identify_cmd lif_identify;
3031 struct ionic_lif_init_cmd lif_init;
3032 struct ionic_lif_reset_cmd lif_reset;
3033
3034 struct ionic_qos_identify_cmd qos_identify;
3035 struct ionic_qos_init_cmd qos_init;
3036 struct ionic_qos_reset_cmd qos_reset;
3037 struct ionic_qos_clear_stats_cmd qos_clear_stats;
3038
3039 struct ionic_q_identify_cmd q_identify;
3040 struct ionic_q_init_cmd q_init;
3041 struct ionic_q_control_cmd q_control;
3042
3043 struct ionic_fw_download_cmd fw_download;
3044 struct ionic_fw_control_cmd fw_control;
3045 };
3046
3047 union ionic_dev_cmd_comp {
3048 u32 words[4];
3049 u8 status;
3050 struct ionic_admin_comp comp;
3051 struct ionic_nop_comp nop;
3052
3053 struct ionic_dev_identify_comp identify;
3054 struct ionic_dev_init_comp init;
3055 struct ionic_dev_reset_comp reset;
3056 struct ionic_dev_getattr_comp getattr;
3057 struct ionic_dev_setattr_comp setattr;
3058
3059 struct ionic_port_identify_comp port_identify;
3060 struct ionic_port_init_comp port_init;
3061 struct ionic_port_reset_comp port_reset;
3062 struct ionic_port_getattr_comp port_getattr;
3063 struct ionic_port_setattr_comp port_setattr;
3064
3065 struct ionic_vf_setattr_comp vf_setattr;
3066 struct ionic_vf_getattr_comp vf_getattr;
3067 struct ionic_vf_ctrl_comp vf_ctrl;
3068
3069 struct ionic_lif_identify_comp lif_identify;
3070 struct ionic_lif_init_comp lif_init;
3071 ionic_lif_reset_comp lif_reset;
3072
3073 struct ionic_qos_identify_comp qos_identify;
3074 ionic_qos_init_comp qos_init;
3075 ionic_qos_reset_comp qos_reset;
3076
3077 struct ionic_q_identify_comp q_identify;
3078 struct ionic_q_init_comp q_init;
3079
3080 ionic_fw_download_comp fw_download;
3081 struct ionic_fw_control_comp fw_control;
3082 };
3083
3084 /**
3085 * struct ionic_hwstamp_regs - Hardware current timestamp registers
3086 * @tick_low: Low 32 bits of hardware timestamp
3087 * @tick_high: High 32 bits of hardware timestamp
3088 */
3089 struct ionic_hwstamp_regs {
3090 u32 tick_low;
3091 u32 tick_high;
3092 };
3093
3094 /**
3095 * union ionic_dev_info_regs - Device info register format (read-only)
3096 * @signature: Signature value of 0x44455649 ('DEVI')
3097 * @version: Current version of info
3098 * @asic_type: Asic type
3099 * @asic_rev: Asic revision
3100 * @fw_status: Firmware status
3101 * bit 0 - 1 = fw running
3102 * bit 4-7 - 4 bit generation number, changes on fw restart
3103 * @fw_heartbeat: Firmware heartbeat counter
3104 * @serial_num: Serial number
3105 * @rsvd_pad1024: reserved byte(s)
3106 * @fw_version: Firmware version
3107 * @hwstamp: Hardware current timestamp registers
3108 * @words: word access to struct contents
3109 */
3110 union ionic_dev_info_regs {
3111 #define IONIC_DEVINFO_FWVERS_BUFLEN 32
3112 #define IONIC_DEVINFO_SERIAL_BUFLEN 32
3113 struct {
3114 u32 signature;
3115 u8 version;
3116 u8 asic_type;
3117 u8 asic_rev;
3118 #define IONIC_FW_STS_F_RUNNING 0x01
3119 #define IONIC_FW_STS_F_GENERATION 0xF0
3120 u8 fw_status;
3121 u32 fw_heartbeat;
3122 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];
3123 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];
3124 u8 rsvd_pad1024[948];
3125 struct ionic_hwstamp_regs hwstamp;
3126 };
3127 u32 words[512];
3128 };
3129
3130 /**
3131 * union ionic_dev_cmd_regs - Device command register format (read-write)
3132 * @doorbell: Device Cmd Doorbell, write-only
3133 * Write a 1 to signal device to process cmd,
3134 * poll done for completion.
3135 * @done: Done indicator, bit 0 == 1 when command is complete
3136 * @cmd: Opcode-specific command bytes
3137 * @comp: Opcode-specific response bytes
3138 * @rsvd: reserved byte(s)
3139 * @data: Opcode-specific side-data
3140 * @words: word access to struct contents
3141 */
3142 union ionic_dev_cmd_regs {
3143 struct {
3144 u32 doorbell;
3145 u32 done;
3146 union ionic_dev_cmd cmd;
3147 union ionic_dev_cmd_comp comp;
3148 u8 rsvd[48];
3149 u32 data[478];
3150 } __packed;
3151 u32 words[512];
3152 };
3153
3154 /**
3155 * union ionic_dev_regs - Device register format for bar 0 page 0
3156 * @info: Device info registers
3157 * @devcmd: Device command registers
3158 * @words: word access to struct contents
3159 */
3160 union ionic_dev_regs {
3161 struct {
3162 union ionic_dev_info_regs info;
3163 union ionic_dev_cmd_regs devcmd;
3164 } __packed;
3165 __le32 words[1024];
3166 };
3167
3168 union ionic_adminq_cmd {
3169 struct ionic_admin_cmd cmd;
3170 struct ionic_nop_cmd nop;
3171 struct ionic_q_identify_cmd q_identify;
3172 struct ionic_q_init_cmd q_init;
3173 struct ionic_q_control_cmd q_control;
3174 struct ionic_lif_setattr_cmd lif_setattr;
3175 struct ionic_lif_getattr_cmd lif_getattr;
3176 struct ionic_lif_setphc_cmd lif_setphc;
3177 struct ionic_rx_mode_set_cmd rx_mode_set;
3178 struct ionic_rx_filter_add_cmd rx_filter_add;
3179 struct ionic_rx_filter_del_cmd rx_filter_del;
3180 struct ionic_rdma_reset_cmd rdma_reset;
3181 struct ionic_rdma_queue_cmd rdma_queue;
3182 struct ionic_fw_download_cmd fw_download;
3183 struct ionic_fw_control_cmd fw_control;
3184 };
3185
3186 union ionic_adminq_comp {
3187 struct ionic_admin_comp comp;
3188 struct ionic_nop_comp nop;
3189 struct ionic_q_identify_comp q_identify;
3190 struct ionic_q_init_comp q_init;
3191 struct ionic_lif_setattr_comp lif_setattr;
3192 struct ionic_lif_getattr_comp lif_getattr;
3193 struct ionic_admin_comp lif_setphc;
3194 struct ionic_rx_filter_add_comp rx_filter_add;
3195 struct ionic_fw_control_comp fw_control;
3196 };
3197
3198 #define IONIC_BARS_MAX 6
3199 #define IONIC_PCI_BAR_DBELL 1
3200 #define IONIC_PCI_BAR_CMB 2
3201
3202 #define IONIC_BAR0_SIZE 0x8000
3203 #define IONIC_BAR2_SIZE 0x800000
3204
3205 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000
3206 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800
3207 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00
3208 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000
3209 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000
3210 #define IONIC_DEV_CMD_DONE 0x00000001
3211
3212 #define IONIC_ASIC_TYPE_CAPRI 0
3213
3214 /**
3215 * struct ionic_doorbell - Doorbell register layout
3216 * @p_index: Producer index
3217 * @ring: Selects the specific ring of the queue to update
3218 * Type-specific meaning:
3219 * ring=0: Default producer/consumer queue
3220 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs
3221 * send events to EQs when armed. EQs send
3222 * interrupts when armed.
3223 * @qid_lo: Queue destination for the producer index and flags (low bits)
3224 * @qid_hi: Queue destination for the producer index and flags (high bits)
3225 * @rsvd2: reserved byte(s)
3226 */
3227 struct ionic_doorbell {
3228 __le16 p_index;
3229 u8 ring;
3230 u8 qid_lo;
3231 __le16 qid_hi;
3232 u16 rsvd2;
3233 };
3234
3235 struct ionic_intr_status {
3236 u32 status[2];
3237 };
3238
3239 struct ionic_notifyq_cmd {
3240 __le32 data; /* Not used but needed for qcq structure */
3241 };
3242
3243 union ionic_notifyq_comp {
3244 struct ionic_notifyq_event event;
3245 struct ionic_link_change_event link_change;
3246 struct ionic_reset_event reset;
3247 struct ionic_heartbeat_event heartbeat;
3248 struct ionic_log_event log;
3249 };
3250
3251 /* Deprecate */
3252 struct ionic_identity {
3253 union ionic_drv_identity drv;
3254 union ionic_dev_identity dev;
3255 union ionic_lif_identity lif;
3256 union ionic_port_identity port;
3257 union ionic_qos_identity qos;
3258 union ionic_q_identity txq;
3259 };
3260
3261 #endif /* _IONIC_IF_H_ */
3262