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Searched refs:INTR_STATUS (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dpio.c239 pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); in hci_pio_cleanup()
276 if (!(pio_reg_read(INTR_STATUS) & STAT_RX_THLD)) in hci_pio_do_rx()
344 if (!(pio_reg_read(INTR_STATUS) & STAT_TX_THLD)) in hci_pio_do_tx()
364 if (!(pio_reg_read(INTR_STATUS) & STAT_TX_THLD)) in hci_pio_do_tx()
506 (pio_reg_read(INTR_STATUS) & STAT_RESP_READY)) { in hci_pio_process_resp()
592 (pio_reg_read(INTR_STATUS) & STAT_CMD_QUEUE_READY)) { in hci_pio_process_cmd()
643 pio_reg_read(INTR_STATUS), in hci_pio_queue_xfer()
719 pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); in hci_pio_dequeue_xfer()
733 if (pio_reg_read(INTR_STATUS) & STAT_RESP_READY) { in hci_pio_err()
766 pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); in hci_pio_err()
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H A Dcore.c77 #define INTR_STATUS 0x20 macro
631 val = reg_read(INTR_STATUS); in i3c_hci_irq_handler()
632 reg_write(INTR_STATUS, val); in i3c_hci_irq_handler()
H A Ddma.c865 status = rh_reg_read(INTR_STATUS); in hci_dma_irq_handler()
870 rh_reg_write(INTR_STATUS, status); in hci_dma_irq_handler()
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hwio.h15 #define INTR_STATUS 0x014 macro
/linux/drivers/i3c/master/
H A Ddw-i3c-master.c119 #define INTR_STATUS 0x3c macro
551 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_set_intr_regs()
1484 status = readl(master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1487 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1494 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1621 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_common_probe()
/linux/drivers/media/platform/nvidia/tegra-vde/
H A Dvde.h30 #define INTR_STATUS 0x18 macro
/linux/drivers/mtd/nand/raw/
H A Ddenali.h208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) macro
H A Ddenali.c111 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); in denali_clear_irq()
132 irq_status = ioread32(denali->reg + INTR_STATUS(i)); in denali_isr()
H A Dcadence-nand-controller.c67 #define INTR_STATUS 0x0110 macro
776 writel_relaxed(irq_status->status, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_clear_interrupt()
787 irq_status->status = readl_relaxed(cdns_ctrl->reg + INTR_STATUS); in cadence_nand_read_int_status()
1231 writel_relaxed(0xFFFFFFFF, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_hw_init()