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Searched refs:INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_sh_mask.h12479 #define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x1 macro
H A Ddce_10_0_sh_mask.h12473 #define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x1 macro
H A Ddce_11_2_sh_mask.h13095 #define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x1 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_sh_mask.h90 #define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK … macro
H A Ddcn_3_5_1_sh_mask.h46644 #define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK … macro
H A Ddcn_3_5_0_sh_mask.h46665 #define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK … macro
H A Ddcn_4_1_0_sh_mask.h54420 #define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK … macro