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Searched refs:INTEL_ARCH_EVENT_MASK (Results 1 – 4 of 4) sorted by relevance

/linux/arch/x86/events/
H A Dperf_event.h104 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && in is_metric_event()
105 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); in is_metric_event()
110 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; in is_slots_event()
681 INTEL_ARCH_EVENT_MASK)
687 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
695 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
698 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
702 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
706 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
710 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
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/linux/arch/x86/include/asm/
H A Dperf_event.h72 #define INTEL_ARCH_EVENT_MASK \ macro
/linux/arch/x86/events/intel/
H A Dcore.c4137 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; in intel_fixup_er()
4812 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); in is_mem_loads_event()
4817 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); in is_mem_loads_aux_event()
4997 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) in intel_pmu_hw_config()
5033 (event->attr.config & ~INTEL_ARCH_EVENT_MASK)) in intel_pmu_hw_config()
5772 return (event->hw.config & INTEL_ARCH_EVENT_MASK) == in erratum_hsw11()
H A Dds.c1731 ((attr->config & INTEL_ARCH_EVENT_MASK) == in pebs_update_adaptive_cfg()