Searched refs:IMX7ULP_CLK_DDR_DIV (Results 1 – 2 of 2) sorted by relevance
45 #define IMX7ULP_CLK_DDR_DIV 32 macro
115 …hws[IMX7ULP_CLK_DDR_DIV] = imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK… in imx7ulp_clk_scg1_init()