Searched refs:IMX7D_PLL_ENET_MAIN_500M_CLK (Results 1 – 3 of 3) sorted by relevance
49 #define IMX7D_PLL_ENET_MAIN_500M_CLK 40 macro
477 …hws[IMX7D_PLL_ENET_MAIN_500M_CLK] = imx_clk_hw_gate("pll_enet_500m_clk", "pll_enet_500m", base + 0… in imx7d_clocks_init()
1341 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;