Searched refs:IMX6UL_CLK_PLL4_AUDIO_DIV (Results 1 – 6 of 6) sorted by relevance
97 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;154 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
193 <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>,196 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
167 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;323 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
101 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
59 #define IMX6UL_CLK_PLL4_AUDIO_DIV 50 macro
234 hws[IMX6UL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", in imx6ul_clocks_init()