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Searched refs:HSYNC (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Ddac507d.c37 sync |= NVVAL(NV507D, DAC_SET_POLARITY, HSYNC, asyh->or.nhsync); in dac507d_ctrl()
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043u11-smarc-du-adv7513.dtso48 pinmux = <RZG2L_PORT_PINMUX(11, 0, 6)>, /* HSYNC */
/linux/Documentation/fb/
H A Dpxafb.rst39 hsynclen:HSYNC == LCCR1_HSW + 1
65 hsync:HSYNC, vsync:VSYNC
H A Dmatroxfb.rst268 left:X left boundary: pixels between end of HSYNC pulse and first pixel.
270 right:X right boundary: pixels between end of picture and start of HSYNC
272 hslen:X length of HSYNC pulse, in pixels. Default is derived from `vesa`
276 sync:X sync. pulse - bit 0 inverts HSYNC polarity, bit 1 VSYNC polarity.
277 If bit 3 (value 0x08) is set, composite sync instead of HSYNC is
/linux/drivers/video/fbdev/i810/
H A Di810_regs.h150 #define HSYNC 0x60008 macro
/linux/include/video/
H A Dsstfb.h161 #define HSYNC 0x0220 macro
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53-mba53.dts133 /* VGA_VSYNC, HSYNC with max drive strength */
H A Dimx6ul-tx6ul-mainboard.dts169 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
H A Dimx6ul-tx6ul.dtsi561 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
594 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
/linux/drivers/pinctrl/renesas/
H A Dpfc-sh7786.c524 GPIO_FN(HSYNC),
/linux/drivers/video/fbdev/
H A Dsstfb.c535 sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1)); in sstfb_set_par()
/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9g45.dtsi283 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
/linux/arch/arm/boot/dts/ti/omap/
H A Dam437x-gp-evm.dts293 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
/linux/drivers/gpu/drm/
H A Ddrm_modes.c1742 MODE_STATUS(HSYNC),