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Searched refs:HHI_VID_PLL_CLK_DIV (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c50 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ macro
140 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
141 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); in meson_vid_pll_set()
204 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
208 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
211 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
213 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
215 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
219 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
221 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
[all …]
/linux/drivers/clk/meson/
H A Dgxbb.c55 #define HHI_VID_PLL_CLK_DIV 0x1a0 macro
1879 .reg_off = HHI_VID_PLL_CLK_DIV,
1884 .reg_off = HHI_VID_PLL_CLK_DIV,
1922 .offset = HHI_VID_PLL_CLK_DIV,
1941 .offset = HHI_VID_PLL_CLK_DIV,
H A Daxg.c74 #define HHI_VID_PLL_CLK_DIV 0x1a0 macro