Home
last modified time | relevance | path

Searched refs:HHI_HDMI_PLL_CNTL (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c99 #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ macro
246 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d); in meson_venci_cvbs_clock_config()
252 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d); in meson_venci_cvbs_clock_config()
255 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, in meson_venci_cvbs_clock_config()
259 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b); in meson_venci_cvbs_clock_config()
267 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
269 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
273 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, in meson_venci_cvbs_clock_config()
276 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7); in meson_venci_cvbs_clock_config()
283 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x3a0504f7); in meson_venci_cvbs_clock_config()
[all …]
/linux/drivers/clk/meson/
H A Dgxbb.c100 #define HHI_HDMI_PLL_CNTL 0x320 macro
198 .reg_off = HHI_HDMI_PLL_CNTL,
203 .reg_off = HHI_HDMI_PLL_CNTL,
208 .reg_off = HHI_HDMI_PLL_CNTL,
218 .reg_off = HHI_HDMI_PLL_CNTL,
223 .reg_off = HHI_HDMI_PLL_CNTL,
246 .reg_off = HHI_HDMI_PLL_CNTL,
251 .reg_off = HHI_HDMI_PLL_CNTL,
256 .reg_off = HHI_HDMI_PLL_CNTL,
272 .reg_off = HHI_HDMI_PLL_CNTL,
[all …]