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Searched refs:HHI_HDMI_CLK_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c89 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ macro
817 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
819 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
821 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
898 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
907 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
916 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
925 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
934 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
H A Dmeson_dw_hdmi.c106 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */ macro
603 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); in meson_dw_hdmi_init()
/linux/drivers/clk/meson/
H A Dmeson8b.h45 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ macro
H A Dgxbb.h57 #define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ macro
H A Dg12a.h75 #define HHI_HDMI_CLK_CNTL 0x1CC macro
H A Dgxbb.c2313 .offset = HHI_HDMI_CLK_CNTL,
2408 .offset = HHI_HDMI_CLK_CNTL,
2424 .offset = HHI_HDMI_CLK_CNTL,
2439 .offset = HHI_HDMI_CLK_CNTL,
H A Dmeson8b.c1703 .offset = HHI_HDMI_CLK_CNTL,
1804 .offset = HHI_HDMI_CLK_CNTL,
1825 .offset = HHI_HDMI_CLK_CNTL,
1842 .offset = HHI_HDMI_CLK_CNTL,
H A Dg12a.c3620 .offset = HHI_HDMI_CLK_CNTL,
3858 .offset = HHI_HDMI_CLK_CNTL,
3874 .offset = HHI_HDMI_CLK_CNTL,
3889 .offset = HHI_HDMI_CLK_CNTL,