Searched refs:HDMI_ACR_N_32 (Results 1 – 15 of 15) sorted by relevance
/linux/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dce_stream_encoder.h | 183 SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ 261 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ 455 uint8_t HDMI_ACR_N_32; member 587 uint32_t HDMI_ACR_N_32; member
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H A D | dce_stream_encoder.c | 1303 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); in dce110_se_setup_hdmi_audio()
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/linux/drivers/gpu/drm/amd/display/dc/dio/dcn32/ |
H A D | dcn32_dio_stream_encoder.h | 78 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
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/linux/drivers/gpu/drm/amd/display/dc/dio/dcn401/ |
H A D | dcn401_dio_stream_encoder.h | 80 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
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/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
H A D | dcn10_stream_encoder.h | 253 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ 469 type HDMI_ACR_N_32;\
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H A D | dcn10_stream_encoder.c | 1289 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); in enc1_se_setup_hdmi_audio()
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/linux/drivers/gpu/drm/amd/display/dc/dcn314/ |
H A D | dcn314_dio_stream_encoder.h |
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/linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
H A D | dcn30_dio_stream_encoder.h | 157 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
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H A D | dcn30_dio_stream_encoder.c | 794 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); in enc3_se_setup_hdmi_audio()
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/linux/drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
H A D | dcn35_dio_stream_encoder.h | 158 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
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/linux/drivers/gpu/drm/radeon/ |
H A D | rv770d.h | 790 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) macro
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H A D | evergreend.h | 644 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) macro
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/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | dce_v6_0.c | 1446 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v6_0_audio_set_acr()
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H A D | dce_v10_0.c | 1495 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v10_0_afmt_update_ACR()
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H A D | dce_v11_0.c | 1544 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v11_0_afmt_update_ACR()
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