Searched refs:HDMI_1_PLL_CFG_3 (Results 1 – 2 of 2) sorted by relevance
91 #define HDMI_1_PLL_CFG_3 0x50 macro
194 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_3, RG_HDMITXPLL_FBKDIV_LOW, fbkdiv_low); in mtk_hdmi_pll_set_hw()