Searched refs:HDMI_1_PLL_CFG_1 (Results 1 – 2 of 2) sorted by relevance
66 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14); in mtk_hdmi_pll_perf()70 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT12_11); in mtk_hdmi_pll_perf()157 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14); in mtk_hdmi_pll_set_hw()177 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT3_2, reserve_3_2_value); in mtk_hdmi_pll_set_hw()180 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT1_0, 0x2); in mtk_hdmi_pll_set_hw()190 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT13, reserve13_value); in mtk_hdmi_pll_set_hw()
75 #define HDMI_1_PLL_CFG_1 0x48 macro