Searched refs:HDMI_1_PLL_CFG_0 (Results 1 – 2 of 2) sorted by relevance
61 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_BP2); in mtk_hdmi_pll_perf() 67 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_IBAND_FIX_EN); in mtk_hdmi_pll_perf() 70 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_HREN, 0x1); in mtk_hdmi_pll_perf() 71 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_LVR_SEL, 0x1); in mtk_hdmi_pll_perf() 73 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_TCL_EN);
68 #define HDMI_1_PLL_CFG_0 0x44 macro