Searched refs:HDMI_1_CFG_0 (Results 1 – 2 of 2) sorted by relevance
345 mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IBIAS_CLK, clk_channel_bias); in mtk_hdmi_pll_drv_setting()348 mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IMP_EN, impedance_en); in mtk_hdmi_pll_drv_setting()364 mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_SER_EN); in mtk_hdmi_pll_prepare()449 mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN); in vtx_signal_en()451 mtk_phy_clear_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN); in vtx_signal_en()
21 #define HDMI_1_CFG_0 0x00 macro