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Searched refs:HALT (Results 1 – 10 of 10) sorted by relevance

/linux/arch/arm/mach-clps711x/
H A Dboard-dt.c22 # define HALT (0x0800) macro
42 DEFINE_RES_MEM(CLPS711X_PHYS_BASE + HALT, SZ_128);
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvpe_v6_1.c80 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, halt ? 1 : 0); in vpe_v6_1_halt()
163 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0); in vpe_v6_1_load_microcode()
H A Dsdma_v5_0.c673 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v5_0_enable()
817 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); in sdma_v5_0_gfx_resume_instance()
1596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v5_0_stop_queue()
H A Dsdma_v5_2.c520 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v5_2_enable()
664 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); in sdma_v5_2_gfx_resume_instance()
1505 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v5_2_stop_queue()
H A Dsdma_v6_0.c468 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v6_0_enable()
601 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); in sdma_v6_0_gfx_resume_instance()
/linux/arch/mips/dec/
H A Dint-handler.S236 FEXPORT(cpu_all_int) # HALT, timers, software junk
/linux/arch/arc/kernel/
H A Dentry-compact.S358 ; If this does happen we simply HALT as it means a BUG !!!
/linux/Documentation/arch/s390/
H A Dvfio-ccw.rst261 Currently, CLEAR SUBCHANNEL and HALT SUBCHANNEL use this region.
423 START SUBCHANNEL, and to issue HALT SUBCHANNEL, CLEAR SUBCHANNEL,
H A Dcds.rst164 ccw_device_halt() function. Some devices require to initially issue a HALT
/linux/drivers/dma/
H A Dhisi_dma.c106 HALT, enumerator