| /linux/arch/arm/mach-clps711x/ |
| H A D | board-dt.c | 22 # define HALT (0x0800) macro
42 DEFINE_RES_MEM(CLPS711X_PHYS_BASE + HALT, SZ_128);
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v2_4.c | 386 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v2_4_enable()
388 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v2_4_enable()
952 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); in sdma_v2_4_soft_reset()
959 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); in sdma_v2_4_soft_reset()
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| H A D | vpe_v6_1.c | 80 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, halt ? 1 : 0); in vpe_v6_1_halt()
163 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0); in vpe_v6_1_load_microcode()
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| H A D | sdma_v5_2.c | 518 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v5_2_enable()
662 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); in sdma_v5_2_gfx_resume_instance()
1526 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v5_2_reset_queue()
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| H A D | sdma_v5_0.c | 702 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v5_0_enable()
846 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); in sdma_v5_0_gfx_resume_instance()
1625 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v5_0_reset_queue()
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| H A D | sdma_v3_0.c | 623 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v3_0_enable()
625 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v3_0_enable()
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| H A D | sdma_v4_4_2.c | 643 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v4_4_2_inst_enable()
986 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); in sdma_v4_4_2_inst_start()
1627 if (!REG_GET_FIELD(RREG32_SDMA(ring->me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT)) in sdma_v4_4_2_reset_queue()
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| H A D | sdma_v7_0.c | 487 mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_MCU_CNTL, HALT, enable ? 0 : 1); in sdma_v7_0_enable()
622 temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, HALT, 0); in sdma_v7_0_gfx_resume_instance()
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| H A D | sdma_v6_0.c | 466 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v6_0_enable()
599 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); in sdma_v6_0_gfx_resume_instance()
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| H A D | sdma_v4_0.c | 1058 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v4_0_enable()
1421 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); in sdma_v4_0_start()
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| /linux/arch/mips/dec/ |
| H A D | int-handler.S | 236 FEXPORT(cpu_all_int) # HALT, timers, software junk
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| /linux/arch/arc/kernel/ |
| H A D | entry-compact.S | 358 ; If this does happen we simply HALT as it means a BUG !!!
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| /linux/Documentation/arch/s390/ |
| H A D | vfio-ccw.rst | 261 Currently, CLEAR SUBCHANNEL and HALT SUBCHANNEL use this region.
423 START SUBCHANNEL, and to issue HALT SUBCHANNEL, CLEAR SUBCHANNEL,
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| H A D | cds.rst | 164 ccw_device_halt() function. Some devices require to initially issue a HALT
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| /linux/drivers/dma/ |
| H A D | hisi_dma.c | 106 HALT, enumerator
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