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Searched refs:GRBM_GFX_INDEX__SE_INDEX__SHIFT (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_powertune.c895 …RITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in vega10_enable_cac_driving_se_didt_config()
946 …RITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in vega10_enable_psm_gc_didt_config()
1007 …RITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in vega10_enable_se_edc_config()
1057 …RITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in vega10_enable_psm_gc_edc_config()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_sh_mask.h640 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT … macro
H A Dgc_9_0_sh_mask.h19844 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT … macro
H A Dgc_9_1_sh_mask.h21151 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h21078 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h13284 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h23230 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h27197 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h15026 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h27816 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h29718 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c1322 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1325 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h4667 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x00000010 macro
H A Dgfx_7_2_sh_mask.h4940 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 macro
H A Dgfx_8_1_sh_mask.h6224 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 macro
H A Dgfx_8_0_sh_mask.h5690 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 macro