Searched refs:GFX_OP_PIPE_CONTROL (Results 1 – 9 of 9) sorted by relevance
66 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()78 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()134 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_flush_rcs()146 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_breadcrumb_rcs()151 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_breadcrumb_rcs()159 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_breadcrumb_rcs()280 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_stall_cs()344 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_emit_flush_rcs()355 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_emit_breadcrumb_rcs()
58 batch[0] = GFX_OP_PIPE_CONTROL(6) | bit_group_0; in __gen8_emit_pipe_control()81 *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0; in __gen8_emit_write_rcs()
344 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_emit_pipeline_flush()360 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen7_emit_pipeline_invalidate()367 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen7_emit_pipeline_invalidate()
104 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; in gen4_emit_flush_rcs()114 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; in gen4_emit_flush_rcs()
287 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) macro
42 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) macro
174 *cs++ = GFX_OP_PIPE_CONTROL(len); in write_timestamp()
131 dw[i++] = GFX_OP_PIPE_CONTROL(6) | bit_group_0; in emit_pipe_control()
297 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,