Home
last modified time | relevance | path

Searched refs:GENMO_WT__VGA_VSYNC_POL_MASK (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7179 #define GENMO_WT__VGA_VSYNC_POL_MASK 0x00000080L macro
H A Ddce_8_0_sh_mask.h10617 #define GENMO_WT__VGA_VSYNC_POL_MASK 0x80 macro
H A Ddce_11_0_sh_mask.h10813 #define GENMO_WT__VGA_VSYNC_POL_MASK 0x80 macro
H A Ddce_10_0_sh_mask.h11001 #define GENMO_WT__VGA_VSYNC_POL_MASK 0x80 macro
H A Ddce_11_2_sh_mask.h12067 #define GENMO_WT__VGA_VSYNC_POL_MASK 0x80 macro
H A Ddce_12_0_sh_mask.h2214 #define GENMO_WT__VGA_VSYNC_POL_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h251 #define GENMO_WT__VGA_VSYNC_POL_MASK … macro
H A Ddcn_1_0_sh_mask.h853 #define GENMO_WT__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_0_1_sh_mask.h346 #define GENMO_WT__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_2_1_sh_mask.h4449 #define GENMO_WT__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_1_2_sh_mask.h346 #define GENMO_WT__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_1_5_sh_mask.h5164 #define GENMO_WT__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_1_6_sh_mask.h361 #define GENMO_WT__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_1_4_sh_mask.h7801 #define GENMO_WT__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_0_2_sh_mask.h264 #define GENMO_WT__VGA_VSYNC_POL_MASK … macro
H A Ddcn_2_0_0_sh_mask.h264 #define GENMO_WT__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_0_0_sh_mask.h245 #define GENMO_WT__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_2_0_sh_mask.h4448 #define GENMO_WT__VGA_VSYNC_POL_MASK … macro