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Searched refs:GENMO_RD__VGA_VSYNC_POL_MASK (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7167 #define GENMO_RD__VGA_VSYNC_POL_MASK 0x00000080L macro
H A Ddce_8_0_sh_mask.h10629 #define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 macro
H A Ddce_11_0_sh_mask.h10825 #define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 macro
H A Ddce_10_0_sh_mask.h11013 #define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 macro
H A Ddce_11_2_sh_mask.h12079 #define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 macro
H A Ddce_12_0_sh_mask.h2256 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h293 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro
H A Ddcn_1_0_sh_mask.h895 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_0_1_sh_mask.h386 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_2_1_sh_mask.h4491 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_1_2_sh_mask.h386 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_1_5_sh_mask.h5206 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_1_6_sh_mask.h403 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_1_4_sh_mask.h7841 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_0_2_sh_mask.h306 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro
H A Ddcn_2_0_0_sh_mask.h306 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_0_0_sh_mask.h287 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro
H A Ddcn_3_2_0_sh_mask.h4490 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro