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Searched refs:GENMO_RD__VGA_HSYNC_POL__SHIFT (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7164 #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x00000006 macro
H A Ddce_8_0_sh_mask.h10628 #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 macro
H A Ddce_11_0_sh_mask.h10824 #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 macro
H A Ddce_10_0_sh_mask.h11012 #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 macro
H A Ddce_11_2_sh_mask.h12078 #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 macro
H A Ddce_12_0_sh_mask.h2249 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h286 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro
H A Ddcn_1_0_sh_mask.h888 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h379 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h4484 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h379 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h5199 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h396 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h7834 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h299 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h299 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h280 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h4483 #define GENMO_RD__VGA_HSYNC_POL__SHIFT … macro