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Searched refs:GENMO_RD__VGA_HSYNC_POL_MASK (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7163 #define GENMO_RD__VGA_HSYNC_POL_MASK 0x00000040L macro
H A Ddce_8_0_sh_mask.h10627 #define GENMO_RD__VGA_HSYNC_POL_MASK 0x40 macro
H A Ddce_11_0_sh_mask.h10823 #define GENMO_RD__VGA_HSYNC_POL_MASK 0x40 macro
H A Ddce_10_0_sh_mask.h11011 #define GENMO_RD__VGA_HSYNC_POL_MASK 0x40 macro
H A Ddce_11_2_sh_mask.h12077 #define GENMO_RD__VGA_HSYNC_POL_MASK 0x40 macro
H A Ddce_12_0_sh_mask.h2255 #define GENMO_RD__VGA_HSYNC_POL_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h292 #define GENMO_RD__VGA_HSYNC_POL_MASK … macro
H A Ddcn_1_0_sh_mask.h894 #define GENMO_RD__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_0_1_sh_mask.h385 #define GENMO_RD__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_2_1_sh_mask.h4490 #define GENMO_RD__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_1_2_sh_mask.h385 #define GENMO_RD__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_1_5_sh_mask.h5205 #define GENMO_RD__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_1_6_sh_mask.h402 #define GENMO_RD__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_1_4_sh_mask.h7840 #define GENMO_RD__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_0_2_sh_mask.h305 #define GENMO_RD__VGA_HSYNC_POL_MASK … macro
H A Ddcn_2_0_0_sh_mask.h305 #define GENMO_RD__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_0_0_sh_mask.h286 #define GENMO_RD__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_2_0_sh_mask.h4489 #define GENMO_RD__VGA_HSYNC_POL_MASK … macro