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Searched refs:GEN7_MISCCPCTL (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/i915/
H A Dvlv_suspend.c149 s->misccpctl = intel_uncore_read(uncore, GEN7_MISCCPCTL); in vlv_save_gunit_s0ix_state()
234 intel_uncore_write(uncore, GEN7_MISCCPCTL, s->misccpctl); in vlv_restore_gunit_s0ix_state()
H A Di915_irq.c152 misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, in ivb_parity_work()
154 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); in ivb_parity_work()
196 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl); in ivb_parity_work()
H A Di915_perf.c2393 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, in hsw_enable_metric_set()
2409 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, in hsw_disable_metric_set()
H A Dintel_gvt_mmio_table.c811 MMIO_D(GEN7_MISCCPCTL); in iterate_bdw_plus_mmio()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c1494 wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, in gen12_gt_workarounds_init()
1537 wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, in dg2_gt_workarounds_init()
1570 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); in xelpg_gt_workarounds_init()
H A Dintel_gt_regs.h705 #define GEN7_MISCCPCTL _MMIO(0x9424) macro