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Searched refs:GCC_VIDEO_AXI1_CLK_ARES (Results 1 – 16 of 16) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dqcom,sar2130p-gcc.h167 #define GCC_VIDEO_AXI1_CLK_ARES 30 macro
H A Dqcom,sm8550-gcc.h218 #define GCC_VIDEO_AXI1_CLK_ARES 34 macro
H A Dqcom,gcc-sm8450.h237 #define GCC_VIDEO_AXI1_CLK_ARES 35 macro
H A Dqcom,qcs8300-gcc.h232 #define GCC_VIDEO_AXI1_CLK_ARES 28 macro
H A Dqcom,sm8650-gcc.h241 #define GCC_VIDEO_AXI1_CLK_ARES 34 macro
H A Dqcom,gcc-sm8350.h250 #define GCC_VIDEO_AXI1_CLK_ARES 36 macro
H A Dqcom,gcc-sm8250.h256 #define GCC_VIDEO_AXI1_CLK_ARES 44 macro
H A Dqcom,sa8775p-gcc.h307 #define GCC_VIDEO_AXI1_CLK_ARES 45 macro
H A Dqcom,gcc-sc8280xp.h480 #define GCC_VIDEO_AXI1_CLK_ARES 78 macro
/linux/drivers/clk/qcom/
H A Dgcc-sar2130p.c2260 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x42024, .bit = 2, .udelay = 1000 },
H A Dgcc-sm8250.c3580 [GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, .bit = 2, .udelay = 150 },
H A Dgcc-sm8450.c3351 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x42020, .bit = 2, .udelay = 1000 },
H A Dgcc-qcs8300.c3542 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x3401c, 2 },
H A Dgcc-sm8350.c3747 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 },
H A Dgcc-sa8775p.c4599 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x3401c, .bit = 2, .udelay = 400 },
H A Dgcc-sc8280xp.c7452 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 },