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Searched refs:GCC_GPU_GPLL0_DIV_CLK_SRC (Results 1 – 25 of 40) sorted by relevance

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/linux/include/dt-bindings/clock/
H A Dqcom,gcc-sc7180.h47 #define GCC_GPU_GPLL0_DIV_CLK_SRC 37 macro
H A Dqcom,sm7150-gcc.h45 #define GCC_GPU_GPLL0_DIV_CLK_SRC 33 macro
H A Dqcom,gcc-qcm2290.h95 #define GCC_GPU_GPLL0_DIV_CLK_SRC 85 macro
H A Dqcom,sar2130p-gcc.h36 #define GCC_GPU_GPLL0_DIV_CLK_SRC 26 macro
H A Dqcom,sm4450-gcc.h44 #define GCC_GPU_GPLL0_DIV_CLK_SRC 34 macro
H A Dqcom,gcc-sm6115.h82 #define GCC_GPU_GPLL0_DIV_CLK_SRC 74 macro
H A Dqcom,gcc-sc7280.h45 #define GCC_GPU_GPLL0_DIV_CLK_SRC 35 macro
H A Dqcom,sm6375-gcc.h109 #define GCC_GPU_GPLL0_DIV_CLK_SRC 98 macro
H A Dqcom,sm8550-gcc.h42 #define GCC_GPU_GPLL0_DIV_CLK_SRC 31 macro
H A Dqcom,gcc-sm6125.h124 #define GCC_GPU_GPLL0_DIV_CLK_SRC 115 macro
H A Dqcom,gcc-sm8450.h56 #define GCC_GPU_GPLL0_DIV_CLK_SRC 44 macro
H A Dqcom,qcs8300-gcc.h56 #define GCC_GPU_GPLL0_DIV_CLK_SRC 46 macro
H A Dqcom,gcc-sdm845.h42 #define GCC_GPU_GPLL0_DIV_CLK_SRC 32 macro
H A Dqcom,gcc-sm8150.h48 #define GCC_GPU_GPLL0_DIV_CLK_SRC 38 macro
H A Dqcom,sm8650-gcc.h44 #define GCC_GPU_GPLL0_DIV_CLK_SRC 33 macro
H A Dqcom,gcc-sm8350.h52 #define GCC_GPU_GPLL0_DIV_CLK_SRC 40 macro
H A Dqcom,gcc-sm8250.h45 #define GCC_GPU_GPLL0_DIV_CLK_SRC 35 macro
H A Dqcom,sa8775p-gcc.h72 #define GCC_GPU_GPLL0_DIV_CLK_SRC 61 macro
H A Dqcom,gcc-sc8180x.h47 #define GCC_GPU_GPLL0_DIV_CLK_SRC 37 macro
H A Dqcom,gcc-sc8280xp.h86 #define GCC_GPU_GPLL0_DIV_CLK_SRC 75 macro
/linux/drivers/clk/qcom/
H A Dgcc-sc7180.c2271 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
H A Dgcc-sar2130p.c2142 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
H A Dgcc-sm4450.c2642 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
H A Dgcc-sm7150.c2785 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
H A Dgcc-qcm2290.c2833 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,

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