Searched refs:GATE_CLK_DDR01_DIV1 (Results 1 – 2 of 2) sorted by relevance
95 #define GATE_CLK_DDR01_DIV1 79 macro
440 SG2042_GATE_FW(GATE_CLK_DDR01_DIV1, "clk_gate_ddr01_div1", "fpll",925 case GATE_CLK_DDR01_DIV1: in sg2042_clk_register_gates_fw()