Searched refs:GATE_CLK_DDR01_DIV0 (Results 1 – 2 of 2) sorted by relevance
98 #define GATE_CLK_DDR01_DIV0 81 macro
437 SG2042_GATE_FW(GATE_CLK_DDR01_DIV0, "clk_gate_ddr01_div0", "dpll0",922 case GATE_CLK_DDR01_DIV0: in sg2042_clk_register_gates_fw()