Searched refs:GATE_CLK_AXI_DDR_DIV1 (Results 1 – 2 of 2) sorted by relevance
94 #define GATE_CLK_AXI_DDR_DIV1 78 macro
463 SG2042_GATE_FW(GATE_CLK_AXI_DDR_DIV1, "clk_gate_axi_ddr_div1", "fpll",943 case GATE_CLK_AXI_DDR_DIV1: in sg2042_clk_register_gates_fw()