Searched refs:GATE_CLK_AXI_DDR_DIV0 (Results 1 – 2 of 2) sorted by relevance
42 #define GATE_CLK_AXI_DDR_DIV0 32 macro
460 SG2042_GATE_FW(GATE_CLK_AXI_DDR_DIV0, "clk_gate_axi_ddr_div0", "mpll",940 case GATE_CLK_AXI_DDR_DIV0: in sg2042_clk_register_gates_fw()