Searched refs:FORMAT_CONTROL (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.c | 60 REG_SET_2(FORMAT_CONTROL, 0, in dpp201_cnv_setup()
71 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp201_cnv_setup()
72 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp201_cnv_setup()
73 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp201_cnv_setup()
74 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp201_cnv_setup()
175 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp201_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| H A D | dcn20_dpp.c | 115 REG_SET_2(FORMAT_CONTROL, 0, in dpp2_cnv_setup()
124 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp2_cnv_setup()
125 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp2_cnv_setup()
126 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp2_cnv_setup()
127 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp2_cnv_setup()
229 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp2_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_ipp.h | 35 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
189 uint32_t FORMAT_CONTROL; member
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp_cm.c | 780 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_full_bypass()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.h | 314 SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \
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