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Searched refs:FLD_GET (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/omapdrm/dss/
H A Ddsi.c51 FLD_GET(dsi_read_reg(dsi, idx), start, end)
745 FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end) in _dsi_print_reset_status()
889 while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) { in dsi_pll_power()
1235 while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1), in dsi_cio_power()
1874 if (FLD_GET(r, 15, 15)) /* VC_BUSY */ in dsi_vc_initial_config()
1977 dt = FLD_GET(val, 5, 0); in dsi_vc_flush_receive_data()
1979 u16 err = FLD_GET(val, 23, 8); in dsi_vc_flush_receive_data()
1983 FLD_GET(val, 23, 8)); in dsi_vc_flush_receive_data()
1986 FLD_GET(val, 23, 8)); in dsi_vc_flush_receive_data()
1989 FLD_GET(val, 23, 8)); in dsi_vc_flush_receive_data()
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H A Dhdmi4_cec.c131 if (FLD_GET(temp, 7, 7) == 0) in hdmi_cec_clear_tx_fifo()
148 if (FLD_GET(temp, 1, 0) == 0) in hdmi_cec_clear_rx_fifo()
222 if (FLD_GET(temp, 4, 4) != 0) { in hdmi_cec_adap_enable()
H A Dpll.c338 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) in wait_for_bit_change()
345 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) in wait_for_bit_change()
H A Dhdmi.h281 FLD_GET(hdmi_read_reg(base, idx), start, end)
H A Ddss.c56 FLD_GET(dss_read_reg(dss, idx), start, end)
1413 pr_info("OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); in dss_probe_hardware()
H A Ddispc.c51 FLD_GET(dispc_read_reg(dispc, idx), start, end)
1200 if (FLD_GET(val, shift, shift) == 1) in dispc_ovl_get_channel_out()
1206 switch (FLD_GET(val, 31, 30)) { in dispc_ovl_get_channel_out()
3159 *lck_div = FLD_GET(l, 23, 16); in dispc_mgr_get_lcd_divisor()
3160 *pck_div = FLD_GET(l, 7, 0); in dispc_mgr_get_lcd_divisor()
3226 pcd = FLD_GET(l, 7, 0); in dispc_mgr_pclk_rate()
3314 lcd = FLD_GET(l, 23, 16); in dispc_dump_clocks()
4671 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); in dispc_bind()
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddsi.c112 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
1198 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end) in _dsi_print_reset_status()
1353 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { in dsi_pll_power()
1760 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), in dsi_cio_power()
2428 if (FLD_GET(r, 15, 15)) /* VC_BUSY */ in dsi_vc_initial_config()
2570 dt = FLD_GET(val, 5, 0); in dsi_vc_flush_receive_data()
2572 u16 err = FLD_GET(val, 23, 8); in dsi_vc_flush_receive_data()
2576 FLD_GET(val, 23, 8)); in dsi_vc_flush_receive_data()
2579 FLD_GET(val, 23, 8)); in dsi_vc_flush_receive_data()
2582 FLD_GET(val, 23, 8)); in dsi_vc_flush_receive_data()
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H A Dpll.c196 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) in wait_for_bit_change()
203 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) in wait_for_bit_change()
H A Ddss.c57 FLD_GET(dss_read_reg(idx), start, end)
1134 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); in dss_bind()
H A Ddispc.c49 FLD_GET(dispc_read_reg(idx), start, end)
984 if (FLD_GET(val, shift, shift) == 1) in dispc_ovl_get_channel_out()
990 switch (FLD_GET(val, 31, 30)) { in dispc_ovl_get_channel_out()
3182 *lck_div = FLD_GET(l, 23, 16); in dispc_mgr_get_lcd_divisor()
3183 *pck_div = FLD_GET(l, 7, 0); in dispc_mgr_get_lcd_divisor()
3227 lcd = FLD_GET(l, 23, 16); in dispc_mgr_lclk_rate()
3268 pcd = FLD_GET(l, 7, 0); in dispc_mgr_pclk_rate()
3353 lcd = FLD_GET(l, 23, 16); in dispc_dump_clocks()
3960 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); in dispc_bind()
H A Dhdmi.h262 FLD_GET(hdmi_read_reg(base, idx), start, end)
H A Ddss.h61 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) macro
/linux/drivers/gpu/drm/tidss/
H A Dtidss_dispc.c484 static u32 FLD_GET(u32 val, u32 start, u32 end) in FLD_GET() function
496 return FLD_GET(dispc_read(dispc, idx), start, end); in REG_GET()
509 return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end); in VID_REG_GET()
523 return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end); in VP_REG_GET()
537 return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end); in OVR_REG_GET()