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Searched refs:FIFO_CONTROL_STATUS_REG (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/gpib/fmh_gpib/
H A Dfmh_gpib.c327 (fifos_read(e_priv, FIFO_CONTROL_STATUS_REG) & in wait_for_rx_fifo_half_full_or_end()
436 fifos_write(e_priv, TX_FIFO_DMA_REQUEST_ENABLE | TX_FIFO_CLEAR, FIFO_CONTROL_STATUS_REG); in fmh_gpib_dma_write()
463 fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG); in fmh_gpib_dma_write()
580 (fifos_read(e_priv, FIFO_CONTROL_STATUS_REG) & in wait_for_tx_fifo_half_empty()
611 fifos_write(e_priv, TX_FIFO_CLEAR, FIFO_CONTROL_STATUS_REG); in fmh_gpib_fifo_write_countable()
619 fifos_write(e_priv, TX_FIFO_HALF_EMPTY_INTERRUPT_ENABLE, FIFO_CONTROL_STATUS_REG); in fmh_gpib_fifo_write_countable()
654 fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG); in fmh_gpib_fifo_write_countable()
754 fifos_write(e_priv, RX_FIFO_DMA_REQUEST_ENABLE | RX_FIFO_CLEAR, FIFO_CONTROL_STATUS_REG); in fmh_gpib_dma_read()
781 fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG); in fmh_gpib_dma_read()
800 while ((fifos_read(e_priv, FIFO_CONTROL_STATUS_REG) & RX_FIFO_EMPTY) == 0) { in fmh_gpib_dma_read()
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H A Dfmh_gpib.h92 FIFO_CONTROL_STATUS_REG = 0x1, enumerator